riscv/rocket-chip
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Revert "replace remaining uses of Vec.fill"

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This reverts commit f7a0d125e83f8ca59d9913bb1db79cef5a6d344a.
This commit is contained in:
Andrew Waterman 2015-09-25 17:02:51 -07:00
parent 0bfb2962a6
commit c3fff12ff0
2 changed files with 2 additions and 2 deletions
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2
rocket/src/main/scala/icache.scala
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@ -202,7 +202,7 @@ class ICache extends FrontendModule
val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid) val tag_rdata = tag_array.read(s0_pgoff(untagBits-1,blockOffBits), !refill_done && s0_valid)
when (refill_done) { when (refill_done) {
val tag = code.encode(s2_tag).toUInt val tag = code.encode(s2_tag).toUInt
tag_array.write(s2_idx, Vec(nWays, tag), Vec.tabulate(nWays)(repl_way === _)) tag_array.write(s2_idx, Vec.fill(nWays)(tag), Vec.tabulate(nWays)(repl_way === _))
} }
val vb_array = Reg(init=Bits(0, nSets*nWays)) val vb_array = Reg(init=Bits(0, nSets*nWays))

2
rocket/src/main/scala/nbdcache.scala
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@ -670,7 +670,7 @@ class DataArray extends L1HellaCacheModule {
for (p <- 0 until resp.size) { for (p <- 0 until resp.size) {
val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles) val array = SeqMem(Vec(Bits(width=encDataBits), rowWords), nSets*refillCycles)
when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) { when (wway_en.orR && io.write.valid && io.write.bits.wmask(p)) {
val data = Vec(rowWords, io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p)) val data = Vec.fill(rowWords)(io.write.bits.data(encDataBits*(p+1)-1,encDataBits*p))
array.write(waddr, data, wway_en.toBools) array.write(waddr, data, wway_en.toBools)
} }
resp(p) := array.read(raddr, rway_en.orR && io.read.valid).toBits resp(p) := array.read(raddr, rway_en.orR && io.read.valid).toBits