riscv/rocket-chip
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Move PRCI from Coreplex to always-on block, where it belongs

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This commit is contained in:
Andrew Waterman
2016-09-14 10:57:01 -07:00
parent 5566bf1b13
commit c3ddff809b
4 changed files with 34 additions and 13 deletions
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10
src/main/scala/coreplex/Coreplex.scala
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@ -59,7 +59,7 @@ abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConf
val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
val debug = new DebugBusIO()(p).flip
val rtcTick = Bool(INPUT)
val prci = Vec(c.nTiles, new PRCITileIO).flip
val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
}
@ -170,14 +170,10 @@ class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp,
debugModule.io.tl <> mmioNetwork.port("int:debug")
debugModule.io.db <> io.debug
val prci = Module(new PRCI)
prci.io.tl <> mmioNetwork.port("int:prci")
prci.io.rtcTick := io.rtcTick
// connect coreplex-internal interrupts to tiles
for (((tile, tileReset), i) <- (tileList zip tileResets) zipWithIndex) {
tileReset := prci.io.tiles(i).reset
tile.io.interrupts := prci.io.tiles(i).interrupts
tileReset := io.prci(i).reset
tile.io.interrupts := io.prci(i).interrupts
tile.io.interrupts.meip := plic.io.harts(plic.cfg.context(i, 'M'))
tile.io.interrupts.seip.foreach(_ := plic.io.harts(plic.cfg.context(i, 'S')))
tile.io.interrupts.debug := debugModule.io.debugInterrupts(i)