riscv/rocket-chip
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Use correct interrupt priority order

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This commit is contained in:
Andrew Waterman
2017-04-21 18:01:32 -07:00
committed by Andrew Waterman
parent bf861293d9
commit c36c171202
2 changed files with 20 additions and 4 deletions
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10
src/main/scala/util/Package.scala
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@ -38,9 +38,17 @@ package object util {
implicit def wcToUInt(c: WideCounter): UInt = c.value
implicit class UIntToAugmentedUInt(val x: UInt) extends AnyVal {
def sextTo(n: Int): UInt =
def sextTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(Fill(n - x.getWidth, x(x.getWidth-1)), x)
}
def padTo(n: Int): UInt = {
require(x.getWidth <= n)
if (x.getWidth == n) x
else Cat(UInt(0, n - x.getWidth), x)
}
def extract(hi: Int, lo: Int): UInt = {
if (hi == lo-1) UInt(0)