From c36b1dfa30290b5009925c719c99e243a7f6313a Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Wed, 20 Mar 2013 14:10:16 -0700 Subject: [PATCH] Cleaned up uncore and coherence interface. Removed defunct broadcast hub. Trait-ified tilelink bundle components. Added generalized mem arbiter. --- uncore/src/coherence.scala | 86 ++-- uncore/src/consts.scala | 6 +- uncore/src/package.scala | 10 +- uncore/src/tilelink.scala | 132 +++++- uncore/src/uncore.scala | 841 ++++++++----------------------------- 5 files changed, 345 insertions(+), 730 deletions(-) diff --git a/uncore/src/coherence.scala b/uncore/src/coherence.scala index f7a75afc..b4c4067f 100644 --- a/uncore/src/coherence.scala +++ b/uncore/src/coherence.scala @@ -34,9 +34,7 @@ abstract class CoherencePolicy { def getVoluntaryWriteback(addr: UFix, client_id: UFix, master_id: UFix): Release def newRelease (incoming: Probe, state: UFix, id: UFix): Release - def messageHasData (rel: Release): Bool - def messageHasData (acq: Acquire): Bool - def messageHasData (grant: Grant): Bool + def messageHasData (rel: SourcedMessage): Bool def messageUpdatesDataArray (reply: Grant): Bool def messageIsUncached(acq: Acquire): Bool @@ -46,8 +44,8 @@ abstract class CoherencePolicy { def getGrantType(a_type: UFix, count: UFix): Bits def getGrantType(rel: Release, count: UFix): Bits def getProbeType(a_type: UFix, global_state: UFix): UFix - def needsMemRead(a_type: UFix, global_state: UFix): Bool - def needsMemWrite(a_type: UFix, global_state: UFix): Bool + def needsOuterRead(a_type: UFix, global_state: UFix): Bool + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool def needsAckReply(a_type: UFix, global_state: UFix): Bool def needsSelfProbe(acq: Acquire): Bool def requiresAck(grant: Grant): Bool @@ -72,13 +70,12 @@ abstract class IncoherentPolicy extends CoherencePolicy { // UNIMPLEMENTED def newStateOnProbe(incoming: Probe, state: UFix): Bits = state def newRelease (incoming: Probe, state: UFix, id: UFix): Release = Release( UFix(0), UFix(0), UFix(0), UFix(0)) - def messageHasData (rel: Release) = Bool(false) def isCoherenceConflict(addr1: Bits, addr2: Bits): Bool = Bool(false) def getGrantType(a_type: UFix, count: UFix): Bits = Bits(0) def getGrantType(rel: Release, count: UFix): Bits = Bits(0) def getProbeType(a_type: UFix, global_state: UFix): UFix = UFix(0) - def needsMemRead(a_type: UFix, global_state: UFix): Bool = Bool(false) - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = Bool(false) + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = Bool(false) + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsAckReply(a_type: UFix, global_state: UFix): Bool = Bool(false) def needsSelfProbe(acq: Acquire) = Bool(false) def requiresAck(grant: Grant) = Bool(true) @@ -134,8 +131,12 @@ class ThreeStateIncoherence extends IncoherentPolicy { def getReleaseTypeOnCacheControl(cmd: Bits): Bits = releaseVoluntaryInvalidateData // TODO def getReleaseTypeOnVoluntaryWriteback(): Bits = releaseVoluntaryInvalidateData - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData( msg: SourcedMessage ) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => Bool(false) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant) = (reply.g_type === grantData) def messageIsUncached(acq: Acquire): Bool = uFixListContains(uncachedAcquireTypeList, acq.a_type) } @@ -221,9 +222,12 @@ class MICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadExclusive) } @@ -259,10 +263,10 @@ class MICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -373,9 +377,12 @@ class MEICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadExclusive) } @@ -413,10 +420,10 @@ class MEICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -534,9 +541,12 @@ class MSICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadShared || reply.g_type === grantReadExclusive) } @@ -571,10 +581,10 @@ class MSICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -693,9 +703,12 @@ class MESICoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { (reply.g_type === grantReadShared || reply.g_type === grantReadExclusive) } @@ -733,10 +746,10 @@ class MESICoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { @@ -871,9 +884,12 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { Release( Mux(needsWriteback(state), with_data, without_data), incoming.addr, id, incoming.master_xact_id) } - def messageHasData (acq: Acquire): Bool = uFixListContains(hasDataAcquireTypeList, acq.a_type) - def messageHasData (rel: Release): Bool = uFixListContains(hasDataReleaseTypeList, rel.r_type) - def messageHasData (grant: Grant): Bool = uFixListContains(hasDataGrantTypeList, grant.g_type) + def messageHasData(msg: SourcedMessage) = msg match { + case acq: Acquire => uFixListContains(hasDataAcquireTypeList, acq.a_type) + case grant: Grant => uFixListContains(hasDataGrantTypeList, grant.g_type) + case rel: Release => uFixListContains(hasDataReleaseTypeList, rel.r_type) + case _ => Bool(false) + } def messageUpdatesDataArray (reply: Grant): Bool = { uFixListContains(List(grantReadShared, grantReadExclusive, grantReadMigratory), reply.g_type) } @@ -913,10 +929,10 @@ class MigratoryCoherence extends CoherencePolicyWithUncached { )) } - def needsMemRead(a_type: UFix, global_state: UFix): Bool = { + def needsOuterRead(a_type: UFix, global_state: UFix): Bool = { (a_type != acquireWriteUncached && a_type != acquireInvalidateOthers) } - def needsMemWrite(a_type: UFix, global_state: UFix): Bool = { + def needsOuterWrite(a_type: UFix, global_state: UFix): Bool = { (a_type === acquireWriteUncached || a_type === acquireWriteWordUncached || a_type === acquireAtomicUncached) } def needsAckReply(a_type: UFix, global_state: UFix): Bool = { diff --git a/uncore/src/consts.scala b/uncore/src/consts.scala index b515c1c8..d348e0ff 100644 --- a/uncore/src/consts.scala +++ b/uncore/src/consts.scala @@ -11,7 +11,7 @@ abstract trait CoherenceConfigConstants { trait UncoreConstants { val NGLOBAL_XACTS = 8 - val MASTER_XACT_ID_BITS = log2Up(NGLOBAL_XACTS) + val MASTER_XACT_ID_MAX_BITS = log2Up(NGLOBAL_XACTS) val CACHE_DATA_SIZE_IN_BYTES = 1 << 6 } @@ -29,7 +29,7 @@ trait TileLinkTypeConstants { trait TileLinkSizeConstants extends TileLinkTypeConstants { - val CLIENT_XACT_ID_BITS = 5 + val CLIENT_XACT_ID_MAX_BITS = 10 val ACQUIRE_WRITE_MASK_BITS = 6 val ACQUIRE_SUBWORD_ADDR_BITS = 3 val ACQUIRE_ATOMIC_OP_BITS = 4 @@ -72,7 +72,7 @@ trait MemoryInterfaceConstants extends UncoreConstants with TileLinkSizeConstants { - val MEM_TAG_BITS = max(CLIENT_XACT_ID_BITS, MASTER_XACT_ID_BITS) + val MEM_TAG_BITS = max(CLIENT_XACT_ID_MAX_BITS, MASTER_XACT_ID_MAX_BITS) val MEM_DATA_BITS = 128 val REFILL_CYCLES = CACHE_DATA_SIZE_IN_BYTES*8/MEM_DATA_BITS } diff --git a/uncore/src/package.scala b/uncore/src/package.scala index 7cce3ff3..492079cc 100644 --- a/uncore/src/package.scala +++ b/uncore/src/package.scala @@ -40,8 +40,6 @@ class BasicCrossbar[T <: Data]()(data: => T)(implicit conf: PhysicalNetworkConfi rdy := arb.ready && (in.bits.header.dst === UFix(i)) }} out <> rrarb.io.out - //out.bits.header.src := rrarb.io.chosen.toUFix - //out.bits.header.dst := UFix(i) }} for(i <- 0 until conf.nEndpoints) { io.in(i).ready := rdyVecs.map(r => r(i)).reduceLeft(_||_) @@ -62,21 +60,23 @@ class LogicalHeader(implicit conf: LogicalNetworkConfiguration) extends Bundle { } object FIFOedLogicalNetworkIOWrapper { - def apply[T <: Data](in: FIFOIO[T])(implicit conf: LogicalNetworkConfiguration) = { - val shim = (new FIFOedLogicalNetworkIOWrapper){ in.bits.clone } + def apply[T <: Data](in: FIFOIO[T], src: UFix = UFix(0), dst: UFix = UFix(0))(implicit conf: LogicalNetworkConfiguration) = { + val shim = (new FIFOedLogicalNetworkIOWrapper(src, dst)){ in.bits.clone } shim.io.in.valid := in.valid shim.io.in.bits := in.bits in.ready := shim.io.in.ready shim.io.out } } -class FIFOedLogicalNetworkIOWrapper[T <: Data]()(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { +class FIFOedLogicalNetworkIOWrapper[T <: Data](src: UFix, dst: UFix)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { val io = new Bundle { val in = (new FIFOIO){ data }.flip val out = (new FIFOIO){(new LogicalNetworkIO){ data }} } io.out.valid := io.in.valid io.out.bits.payload := io.in.bits + io.out.bits.header.dst := dst + io.out.bits.header.src := src io.in.ready := io.out.ready } diff --git a/uncore/src/tilelink.scala b/uncore/src/tilelink.scala index 73bf8aff..c16f8c9b 100644 --- a/uncore/src/tilelink.scala +++ b/uncore/src/tilelink.scala @@ -3,20 +3,30 @@ package uncore import Chisel._ import Constants._ -class PhysicalAddress extends Bundle { +trait HasPhysicalAddress extends Bundle { val addr = UFix(width = PADDR_BITS - OFFSET_BITS) } -class MemData extends Bundle { +trait HasClientTransactionId extends Bundle { + val client_xact_id = Bits(width = CLIENT_XACT_ID_MAX_BITS) +} + +trait HasMasterTransactionId extends Bundle { + val master_xact_id = Bits(width = MASTER_XACT_ID_MAX_BITS) +} + +trait HasMemData extends Bundle { val data = Bits(width = MEM_DATA_BITS) } -class MemReqCmd extends PhysicalAddress { +class MemData extends Bundle with HasMemData + +class MemReqCmd extends Bundle with HasPhysicalAddress { val rw = Bool() val tag = Bits(width = MEM_TAG_BITS) } -class MemResp extends MemData { +class MemResp extends Bundle with HasMemData { val tag = Bits(width = MEM_TAG_BITS) } @@ -32,9 +42,12 @@ class ioMemPipe extends Bundle { val resp = (new PipeIO) { new MemResp() }.flip } -class Acquire extends PhysicalAddress { +trait SourcedMessage extends Bundle +trait ClientSourcedMessage extends SourcedMessage +trait MasterSourcedMessage extends SourcedMessage + +class Acquire extends ClientSourcedMessage with HasPhysicalAddress with HasClientTransactionId { val a_type = Bits(width = ACQUIRE_TYPE_MAX_BITS) - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) val write_mask = Bits(width = ACQUIRE_WRITE_MASK_BITS) val subword_addr = Bits(width = ACQUIRE_SUBWORD_ADDR_BITS) val atomic_opcode = Bits(width = ACQUIRE_ATOMIC_OP_BITS) @@ -47,6 +60,9 @@ object Acquire acq.a_type := a_type acq.addr := addr acq.client_xact_id := client_xact_id + acq.write_mask := Bits(0, width = ACQUIRE_WRITE_MASK_BITS) + acq.subword_addr := Bits(0, width = ACQUIRE_SUBWORD_ADDR_BITS) + acq.atomic_opcode := Bits(0, width = ACQUIRE_ATOMIC_OP_BITS) acq } def apply(a_type: Bits, addr: UFix, client_xact_id: UFix, write_mask: Bits) = { @@ -55,6 +71,8 @@ object Acquire acq.addr := addr acq.client_xact_id := client_xact_id acq.write_mask := write_mask + acq.subword_addr := Bits(0, width = ACQUIRE_SUBWORD_ADDR_BITS) + acq.atomic_opcode := Bits(0, width = ACQUIRE_ATOMIC_OP_BITS) acq } def apply(a_type: Bits, addr: UFix, client_xact_id: UFix, subword_addr: UFix, atomic_opcode: UFix) = { @@ -64,15 +82,15 @@ object Acquire acq.client_xact_id := client_xact_id acq.subword_addr := subword_addr acq.atomic_opcode := atomic_opcode + acq.write_mask := Bits(0, width = ACQUIRE_WRITE_MASK_BITS) acq } } -class AcquireData extends MemData +class AcquireData extends ClientSourcedMessage with HasMemData -class Probe extends PhysicalAddress { +class Probe extends MasterSourcedMessage with HasPhysicalAddress with HasMasterTransactionId { val p_type = Bits(width = PROBE_TYPE_MAX_BITS) - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } object Release @@ -86,35 +104,105 @@ object Release rel } } -class Release extends PhysicalAddress { +class Release extends ClientSourcedMessage with HasPhysicalAddress with HasClientTransactionId with HasMasterTransactionId { val r_type = Bits(width = RELEASE_TYPE_MAX_BITS) - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } -class ReleaseData extends MemData +class ReleaseData extends ClientSourcedMessage with HasMemData -class Grant extends MemData { +class Grant extends MasterSourcedMessage with HasMemData with HasClientTransactionId with HasMasterTransactionId { val g_type = Bits(width = GRANT_TYPE_MAX_BITS) - val client_xact_id = Bits(width = CLIENT_XACT_ID_BITS) - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) } -class GrantAck extends Bundle { - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) -} +class GrantAck extends ClientSourcedMessage with HasMasterTransactionId abstract class DirectionalFIFOIO[T <: Data]()(data: => T) extends FIFOIO()(data) class ClientSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) class MasterSourcedIO[T <: Data]()(data: => T) extends DirectionalFIFOIO()(data) {flip()} -class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { +class UncachedTileLinkIO(implicit conf: LogicalNetworkConfiguration) extends Bundle { val acquire = (new ClientSourcedIO){(new LogicalNetworkIO){new Acquire }} val acquire_data = (new ClientSourcedIO){(new LogicalNetworkIO){new AcquireData }} + val grant = (new MasterSourcedIO) {(new LogicalNetworkIO){new Grant }} + val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }} + override def clone = { new UncachedTileLinkIO().asInstanceOf[this.type] } +} + +class TileLinkIO(implicit conf: LogicalNetworkConfiguration) extends UncachedTileLinkIO()(conf) { val probe = (new MasterSourcedIO){(new LogicalNetworkIO){new Probe }} val release = (new ClientSourcedIO){(new LogicalNetworkIO){new Release }} val release_data = (new ClientSourcedIO){(new LogicalNetworkIO){new ReleaseData }} - val grant = (new MasterSourcedIO){(new LogicalNetworkIO){new Grant }} - val grant_ack = (new ClientSourcedIO){(new LogicalNetworkIO){new GrantAck }} override def clone = { new TileLinkIO().asInstanceOf[this.type] } } + +object UncachedTileLinkIOArbiterShim { + def apply[T <: HasClientTransactionId](in: ClientSourcedIO[LogicalNetworkIO[T]], id: Int, max: Int)(implicit lconf: LogicalNetworkConfiguration) = { + val shim = (new UncachedTileLinkIOArbiterShim(id, max)){in.bits.payload.clone} + shim.io.in <> in + shim.io.out + } +} +class UncachedTileLinkIOArbiterShim[T <: HasClientTransactionId](id: Int, max: Int)(data: => T)(implicit lconf: LogicalNetworkConfiguration) extends Component { + val io = new Bundle { + val in = (new ClientSourcedIO){(new LogicalNetworkIO){ data }}.flip + val out = (new ClientSourcedIO){(new LogicalNetworkIO){ data }} + } + io.out.bits := io.in.bits + io.out.bits.payload.client_xact_id := Cat(io.in.bits.payload.client_xact_id, UFix(id, log2Up(max))) + io.out.valid := io.in.valid + io.in.ready := io.out.ready +} + + +class UncachedTileLinkIOArbiter(n: Int)(implicit conf: LogicalNetworkConfiguration) extends Component { + val io = new Bundle { + val in = Vec(n) { new UncachedTileLinkIO }.flip + val out = new UncachedTileLinkIO + } + + val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) + val mem_cnt_next = mem_cnt + UFix(1) + val locked = Reg(resetVal = Bool(false)) + val lock_idx = Reg(resetVal = UFix(n)) + + when(io.out.acquire_data.valid && io.out.acquire_data.ready) { + mem_cnt := mem_cnt_next + when(!locked) { + locked := Bool(true) + lock_idx := Vec(io.in.map{ in => in.acquire_data.ready && in.acquire_data.valid}){Bool()}.indexWhere{i: Bool => i} + } + when(mem_cnt_next === UFix(0)) { + locked := Bool(false) + } + } + + val acqd_grant = ArbiterCtrl(io.in.map(_.acquire_data.valid)) + (0 until n).map(i => io.in(i).acquire_data.ready := Mux(locked, UFix(i) === lock_idx, acqd_grant(i)) && io.out.acquire_data.ready) + var acqd_bits = io.in(n-1).acquire_data.bits + for (i <- n-2 to 0 by -1) { + acqd_bits = Mux(io.in(i).acquire_data.valid, io.in(i).acquire_data.bits, acqd_bits) + } + val locked_req = io.in(lock_idx).acquire_data + io.out.acquire_data.bits := Mux(locked, locked_req.bits, acqd_bits) + io.out.acquire_data.valid := Mux(locked, locked_req.valid, io.in.map(_.acquire_data.valid).reduce(_||_)) + + val acq_arb = (new Arbiter(n)){ (new LogicalNetworkIO){new Acquire} } + io.out.acquire <> acq_arb.io.out + io.in.map(_.acquire).zipWithIndex.map{ case(acq, id) => UncachedTileLinkIOArbiterShim(acq, id, n) }.zip(acq_arb.io.in).map{ case (req, arb) => req <> arb} + + val grant_ack_arb = (new Arbiter(n)){ (new LogicalNetworkIO){new GrantAck} } + io.out.grant_ack <> grant_ack_arb.io.out + grant_ack_arb.io.in zip io.in map { case (arb, req) => arb <> req.grant_ack } + + io.out.grant.ready := Bool(false) + for (i <- 0 until n) { + val tag = io.out.grant.bits.payload.client_xact_id + io.in(i).grant.valid := Bool(false) + when (tag(log2Up(n)-1,0) === UFix(i)) { + io.in(i).grant.valid := io.out.grant.valid + io.out.grant.ready := io.in(i).grant.ready + } + io.in(i).grant.bits := io.out.grant.bits + io.in(i).grant.bits.payload.client_xact_id := tag >> UFix(log2Up(n)) + } +} diff --git a/uncore/src/uncore.scala b/uncore/src/uncore.scala index 5609b701..14467f7b 100644 --- a/uncore/src/uncore.scala +++ b/uncore/src/uncore.scala @@ -3,688 +3,199 @@ package uncore import Chisel._ import Constants._ -class TrackerProbeData(implicit conf: CoherenceHubConfiguration) extends Bundle { +class TrackerProbeData(implicit conf: UncoreConfiguration) extends Bundle { val client_id = Bits(width = conf.ln.idBits) } -class TrackerAllocReq(implicit conf: CoherenceHubConfiguration) extends Bundle { +class TrackerAllocReq(implicit conf: UncoreConfiguration) extends Bundle { val acquire = new Acquire() val client_id = Bits(width = conf.ln.idBits) override def clone = { new TrackerAllocReq().asInstanceOf[this.type] } } class TrackerDependency extends Bundle { - val master_xact_id = Bits(width = MASTER_XACT_ID_BITS) + val master_xact_id = Bits(width = MASTER_XACT_ID_MAX_BITS) } -class XactTrackerBroadcast(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component { - val co = conf.co - val io = new Bundle { - val alloc_req = (new FIFOIO) { new TrackerAllocReq }.flip - val p_data = (new PipeIO) { new TrackerProbeData }.flip - val can_alloc = Bool(INPUT) - val grant_ack = Bool(INPUT) - val release_cnt_dec = Bits(INPUT, conf.ln.nClients) - val probe_cnt_inc = Bits(INPUT, conf.ln.nClients) - val tile_incoherent = Bits(INPUT, conf.ln.nClients) - val release_data = (new PipeIO) { new ReleaseData }.flip - val acquire_data = (new PipeIO) { new AcquireData }.flip - val sent_grant_ack = Bool(INPUT) - val release_data_dep = (new PipeIO) { new TrackerDependency }.flip - val acquire_data_dep = (new PipeIO) { new TrackerDependency }.flip - - val mem_req_cmd = (new FIFOIO) { new MemReqCmd } - val mem_req_data = (new FIFOIO) { new MemData } - val mem_req_lock = Bool(OUTPUT) - val probe = (new FIFOIO) { new Probe } - val busy = Bool(OUTPUT) - val addr = Bits(OUTPUT, PADDR_BITS - OFFSET_BITS) - val init_client_id = Bits(OUTPUT, conf.ln.idBits) - val release_client_id = Bits(OUTPUT, conf.ln.idBits) - val client_xact_id = Bits(OUTPUT, CLIENT_XACT_ID_BITS) - val sharer_count = Bits(OUTPUT, conf.ln.idBits+1) - val a_type = Bits(OUTPUT, ACQUIRE_TYPE_MAX_BITS) - val push_probe = Bits(OUTPUT, conf.ln.nClients) - val pop_release = Bits(OUTPUT, conf.ln.nClients) - val pop_release_data = Bits(OUTPUT, conf.ln.nClients) - val pop_release_dep = Bits(OUTPUT, conf.ln.nClients) - val pop_acquire = Bits(OUTPUT, conf.ln.nClients) - val pop_acquire_data = Bits(OUTPUT, conf.ln.nClients) - val pop_acquire_dep = Bits(OUTPUT, conf.ln.nClients) - val send_grant_ack = Bool(OUTPUT) - } - - def doMemReqWrite(req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: PipeIO[MemData], trigger: Bool, cmd_sent: Bool, pop_data: Bits, pop_dep: Bits, at_front_of_dep_queue: Bool, client_id: UFix) { - req_cmd.bits.rw := Bool(true) - req_data.bits := data.bits - when(req_cmd.ready && req_cmd.valid) { - cmd_sent := Bool(true) - } - when (at_front_of_dep_queue) { - req_cmd.valid := !cmd_sent && req_data.ready && data.valid - lock := data.valid || cmd_sent - when (req_cmd.ready || cmd_sent) { - req_data.valid := data.valid - when(req_data.ready) { - pop_data := UFix(1) << client_id - when (data.valid) { - mem_cnt := mem_cnt_next - when(mem_cnt === UFix(REFILL_CYCLES-1)) { - pop_dep := UFix(1) << client_id - trigger := Bool(false) - } - } - } - } - } - } - - def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) { - req_cmd.valid := Bool(true) - req_cmd.bits.rw := Bool(false) - when(req_cmd.ready) { - trigger := Bool(false) - } - } - - val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() } - val state = Reg(resetVal = s_idle) - val xact = Reg{ new Acquire } - val init_client_id_ = Reg{ Bits() } - val release_count = if (conf.ln.nClients == 1) UFix(0) else Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) - val probe_flags = Reg(resetVal = Bits(0, width = conf.ln.nClients)) - val release_client_id_ = Reg{ Bits() } - val x_needs_read = Reg(resetVal = Bool(false)) - val acquire_data_needs_write = Reg(resetVal = Bool(false)) - val release_data_needs_write = Reg(resetVal = Bool(false)) - val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) - val mem_cnt_next = mem_cnt + UFix(1) - val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) - val probe_initial_flags = Bits(width = conf.ln.nClients) - probe_initial_flags := Bits(0) - if (conf.ln.nClients > 1) { - val probe_self = co.needsSelfProbe(io.alloc_req.bits.acquire) - val probe_self_flag = Mux(probe_self, Bits(0), UFixToOH(io.alloc_req.bits.client_id(log2Up(conf.ln.nClients)-1,0))) - probe_initial_flags := ~(io.tile_incoherent | probe_self_flag) - } - - io.busy := state != s_idle - io.addr := xact.addr - io.init_client_id := init_client_id_ - io.release_client_id := release_client_id_ - io.client_xact_id := xact.client_xact_id - io.sharer_count := UFix(conf.ln.nClients) // TODO: Broadcast only - io.a_type := xact.a_type - - io.mem_req_cmd.valid := Bool(false) - io.mem_req_cmd.bits.rw := Bool(false) - io.mem_req_cmd.bits.addr := xact.addr - io.mem_req_cmd.bits.tag := UFix(id) - io.mem_req_data.valid := Bool(false) - io.mem_req_data.bits.data := UFix(0) - io.mem_req_lock := Bool(false) - io.probe.valid := Bool(false) - io.probe.bits.p_type := co.getProbeType(xact.a_type, UFix(0)) - io.probe.bits.master_xact_id := UFix(id) - io.probe.bits.addr := xact.addr - io.push_probe := Bits(0, width = conf.ln.nClients) - io.pop_release := Bits(0, width = conf.ln.nClients) - io.pop_release_data := Bits(0, width = conf.ln.nClients) - io.pop_release_dep := Bits(0, width = conf.ln.nClients) - io.pop_acquire := Bits(0, width = conf.ln.nClients) - io.pop_acquire_data := Bits(0, width = conf.ln.nClients) - io.pop_acquire_dep := Bits(0, width = conf.ln.nClients) - io.send_grant_ack := Bool(false) - - switch (state) { - is(s_idle) { - when( io.alloc_req.valid && io.can_alloc ) { - xact := io.alloc_req.bits.acquire - init_client_id_ := io.alloc_req.bits.client_id - acquire_data_needs_write := co.messageHasData(io.alloc_req.bits.acquire) - x_needs_read := co.needsMemRead(io.alloc_req.bits.acquire.a_type, UFix(0)) - probe_flags := probe_initial_flags - mem_cnt := UFix(0) - p_w_mem_cmd_sent := Bool(false) - x_w_mem_cmd_sent := Bool(false) - io.pop_acquire := UFix(1) << io.alloc_req.bits.client_id - if(conf.ln.nClients > 1) { - release_count := PopCount(probe_initial_flags) - state := Mux(probe_initial_flags.orR, s_probe, s_mem) - } else state := s_mem - } - } - is(s_probe) { - when(probe_flags.orR) { - io.push_probe := probe_flags - io.probe.valid := Bool(true) - } - when(io.probe_cnt_inc.orR) { - probe_flags := probe_flags & ~io.probe_cnt_inc // unflag sent reqs - } - when(io.release_cnt_dec.orR) { - val dec = PopCount(io.release_cnt_dec) - io.pop_release := io.release_cnt_dec - if(conf.ln.nClients > 1) release_count := release_count - dec - when(release_count === dec) { - state := s_mem - } - } - when(io.p_data.valid) { - release_data_needs_write := Bool(true) - release_client_id_ := io.p_data.bits.client_id - } - } - is(s_mem) { - when (release_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.release_data, - release_data_needs_write, - p_w_mem_cmd_sent, - io.pop_release_data, - io.pop_release_dep, - io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id)), - release_client_id_) - } . elsewhen(acquire_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.acquire_data, - acquire_data_needs_write, - x_w_mem_cmd_sent, - io.pop_acquire_data, - io.pop_acquire_dep, - io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id)), - init_client_id_) - } . elsewhen (x_needs_read) { - doMemReqRead(io.mem_req_cmd, x_needs_read) - } . otherwise { - state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack, s_busy) - } - } - is(s_ack) { - io.send_grant_ack := Bool(true) - when(io.sent_grant_ack) { state := s_busy } - } - is(s_busy) { // Nothing left to do but wait for transaction to complete - when (io.grant_ack) { - state := s_idle - } - } - } -} - -case class CoherenceHubConfiguration(co: CoherencePolicy, ln: LogicalNetworkConfiguration) - -class CoherenceHubAdapter(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { - val io = new Bundle { - val net = (new TileLinkIO).flip - val hub = Vec(conf.nClients) { new TileLinkIO } - } - - val netClientProducedSubBundles = io.net.getClass.getMethods.filter( x => - classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io.net).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] } - val netMasterProducedSubBundles = io.net.getClass.getMethods.filter( x => - classOf[MasterSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io.net).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]] } - - val hubClientProducedSubBundles = io.hub.map{ io => { - io.getClass.getMethods.filter( x => - classOf[ClientSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io).asInstanceOf[ClientSourcedIO[LogicalNetworkIO[Data]]] }}}.transpose - val hubMasterProducedSubBundles = io.hub.map{ io => { - io.getClass.getMethods.filter( x => - classOf[MasterSourcedIO[Data]].isAssignableFrom(x.getReturnType)).map{ m => - m.invoke(io).asInstanceOf[MasterSourcedIO[LogicalNetworkIO[Data]]] }}}.transpose - - hubMasterProducedSubBundles.zip(netMasterProducedSubBundles).foreach{ case(hub, net) => { - net.bits.header.src := UFix(0) - net.bits.header.dst := Vec(hub.map(_.valid)){Bool()}.indexWhere{s: Bool => s} - net.bits.payload := hub(0).bits.payload - net.valid := hub.map(_.valid).fold(Bool(false))(_||_) - hub.foreach( _.ready := net.ready) - }} - hubClientProducedSubBundles.zip(netClientProducedSubBundles).foreach{ case(hub, net) => { - hub.foreach(_.bits.header := net.bits.header) - hub.zipWithIndex.foreach{ case(h,i) => h.valid := (net.bits.header.src === UFix(i)) && net.valid } - hub.foreach(_.bits.payload := net.bits.payload) - net.ready := hub.map(_.ready).fold(Bool(false))(_||_) - }} -} - -abstract class CoherenceHub(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { - val io = new Bundle { - val tiles = Vec(conf.nClients) { new TileLinkIO }.flip - val incoherent = Vec(conf.nClients) { Bool() }.asInput - val mem = new ioMem - } -} - -class CoherenceHubNull(implicit conf: CoherenceHubConfiguration) extends CoherenceHub()(conf.ln) -{ - val co = conf.co.asInstanceOf[ThreeStateIncoherence] - - val acquire = io.tiles(0).acquire - val is_write = acquire.bits.payload.a_type === co.acquireWriteback - acquire.ready := io.mem.req_cmd.ready && !(is_write && io.mem.resp.valid) //stall write req/resp to handle previous read resp - io.mem.req_cmd.valid := acquire.valid && !(is_write && io.mem.resp.valid) - io.mem.req_cmd.bits.rw := is_write - io.mem.req_cmd.bits.tag := acquire.bits.payload.client_xact_id - io.mem.req_cmd.bits.addr := acquire.bits.payload.addr - io.mem.req_data <> io.tiles(0).acquire_data - - val grant = io.tiles(0).grant - grant.bits.payload.g_type := Mux(io.mem.resp.valid, co.grantData, co.grantAck) - grant.bits.payload.client_xact_id := Mux(io.mem.resp.valid, io.mem.resp.bits.tag, acquire.bits.payload.client_xact_id) - grant.bits.payload.master_xact_id := UFix(0) // don't care - grant.bits.payload.data := io.mem.resp.bits.data - grant.valid := io.mem.resp.valid || acquire.valid && is_write && io.mem.req_cmd.ready - - io.tiles(0).grant_ack.ready := Bool(true) - io.tiles(0).probe.valid := Bool(false) - io.tiles(0).release.ready := Bool(true) - io.tiles(0).release_data.ready := Bool(true) -} - - -class CoherenceHubBroadcast(implicit conf: CoherenceHubConfiguration) extends CoherenceHub()(conf.ln) -{ - implicit val lnConf = conf.ln - val co = conf.co - val trackerList = (0 until NGLOBAL_XACTS).map(new XactTrackerBroadcast(_)) - - val busy_arr = Vec(NGLOBAL_XACTS){ Bool() } - val addr_arr = Vec(NGLOBAL_XACTS){ Bits(width=PADDR_BITS-OFFSET_BITS) } - val init_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } - val client_xact_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=CLIENT_XACT_ID_BITS) } - val a_type_arr = Vec(NGLOBAL_XACTS){ Bits(width=ACQUIRE_TYPE_MAX_BITS) } - val sh_count_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } - val send_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } - - val do_free_arr = Vec(NGLOBAL_XACTS){ Bool() } - val release_cnt_dec_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} } - val probe_cnt_inc_arr = VecBuf(NGLOBAL_XACTS){ Vec(conf.ln.nClients){ Bool()} } - val sent_grant_ack_arr = Vec(NGLOBAL_XACTS){ Bool() } - val p_data_client_id_arr = Vec(NGLOBAL_XACTS){ Bits(width=conf.ln.idBits) } - val p_data_valid_arr = Vec(NGLOBAL_XACTS){ Bool() } - - for( i <- 0 until NGLOBAL_XACTS) { - val t = trackerList(i).io - busy_arr(i) := t.busy - addr_arr(i) := t.addr - init_client_id_arr(i) := t.init_client_id - client_xact_id_arr(i) := t.client_xact_id - a_type_arr(i) := t.a_type - sh_count_arr(i) := t.sharer_count - send_grant_ack_arr(i) := t.send_grant_ack - t.grant_ack := do_free_arr(i) - t.p_data.bits.client_id := p_data_client_id_arr(i) - t.p_data.valid := p_data_valid_arr(i) - t.release_cnt_dec := release_cnt_dec_arr(i).toBits - t.probe_cnt_inc := probe_cnt_inc_arr(i).toBits - t.tile_incoherent := io.incoherent.toBits - t.sent_grant_ack := sent_grant_ack_arr(i) - do_free_arr(i) := Bool(false) - sent_grant_ack_arr(i) := Bool(false) - p_data_client_id_arr(i) := Bits(0, width = conf.ln.idBits) - p_data_valid_arr(i) := Bool(false) - for( j <- 0 until conf.ln.nClients) { - release_cnt_dec_arr(i)(j) := Bool(false) - probe_cnt_inc_arr(i)(j) := Bool(false) - } - } - - val release_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth must >= NPRIMARY - val acquire_data_dep_list = List.fill(conf.ln.nClients)((new Queue(NGLOBAL_XACTS)){new TrackerDependency}) // depth should >= NPRIMARY - - // Free finished transactions - for( j <- 0 until conf.ln.nClients ) { - val ack = io.tiles(j).grant_ack - when (ack.valid) { - do_free_arr(ack.bits.payload.master_xact_id) := Bool(true) - } - ack.ready := Bool(true) - } - - // Reply to initial requestor - // Forward memory responses from mem to tile or arbitrate to ack - val mem_idx = io.mem.resp.bits.tag - val ack_idx = PriorityEncoder(send_grant_ack_arr.toBits) - for( j <- 0 until conf.ln.nClients ) { - val rep = io.tiles(j).grant - rep.bits.payload.g_type := UFix(0) - rep.bits.payload.client_xact_id := UFix(0) - rep.bits.payload.master_xact_id := UFix(0) - rep.bits.payload.data := io.mem.resp.bits.data - rep.valid := Bool(false) - when(io.mem.resp.valid && (UFix(j) === init_client_id_arr(mem_idx))) { - rep.bits.payload.g_type := co.getGrantType(a_type_arr(mem_idx), sh_count_arr(mem_idx)) - rep.bits.payload.client_xact_id := client_xact_id_arr(mem_idx) - rep.bits.payload.master_xact_id := mem_idx - rep.valid := Bool(true) - } . otherwise { - rep.bits.payload.g_type := co.getGrantType(a_type_arr(ack_idx), sh_count_arr(ack_idx)) - rep.bits.payload.client_xact_id := client_xact_id_arr(ack_idx) - rep.bits.payload.master_xact_id := ack_idx - when (UFix(j) === init_client_id_arr(ack_idx)) { - rep.valid := send_grant_ack_arr.toBits.orR - sent_grant_ack_arr(ack_idx) := rep.ready - } - } - } - io.mem.resp.ready := io.tiles(init_client_id_arr(mem_idx)).grant.ready - - // Create an arbiter for the one memory port - // We have to arbitrate between the different trackers' memory requests - // and once we have picked a request, get the right write data - val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS)) { new MemReqCmd() } - val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS)) { new MemData() } - for( i <- 0 until NGLOBAL_XACTS ) { - mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd - mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data - mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock - } - io.mem.req_cmd <> Queue(mem_req_cmd_arb.io.out) - io.mem.req_data <> Queue(mem_req_data_arb.io.out) - - // Handle probe replies, which may or may not have data - for( j <- 0 until conf.ln.nClients ) { - val release = io.tiles(j).release - val release_data = io.tiles(j).release_data - val idx = release.bits.payload.master_xact_id - val pop_releases = trackerList.map(_.io.pop_release(j).toBool) - val do_pop = foldR(pop_releases)(_ || _) - release.ready := Bool(true) - release_data_dep_list(j).io.enq.valid := release.valid && co.messageHasData(release.bits.payload) - release_data_dep_list(j).io.enq.bits.master_xact_id := release.bits.payload.master_xact_id - release_data.ready := foldR(trackerList.map(_.io.pop_release_data(j)))(_ || _) - when (release.valid && co.messageHasData(release.bits.payload)) { - p_data_valid_arr(idx) := Bool(true) - p_data_client_id_arr(idx) := UFix(j) - } - release_data_dep_list(j).io.deq.ready := foldR(trackerList.map(_.io.pop_release_dep(j).toBool))(_||_) - } - for( i <- 0 until NGLOBAL_XACTS ) { - trackerList(i).io.release_data.valid := io.tiles(trackerList(i).io.release_client_id).release_data.valid - trackerList(i).io.release_data.bits := io.tiles(trackerList(i).io.release_client_id).release_data.bits.payload - - trackerList(i).io.release_data_dep.valid := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.valid)) - trackerList(i).io.release_data_dep.bits := MuxLookup(trackerList(i).io.release_client_id, release_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> release_data_dep_list(j).io.deq.bits)) - - for( j <- 0 until conf.ln.nClients) { - val release = io.tiles(j).release - release_cnt_dec_arr(i)(j) := release.valid && (release.bits.payload.master_xact_id === UFix(i)) - } - } - - // Handle transaction initiation requests - // Only one allocation per cycle - // Init requests may or may not have data - val alloc_arb = (new Arbiter(NGLOBAL_XACTS)) { Bool() } - val init_arb = (new Arbiter(conf.ln.nClients)) { new TrackerAllocReq } - for( i <- 0 until NGLOBAL_XACTS ) { - alloc_arb.io.in(i).valid := !trackerList(i).io.busy - trackerList(i).io.can_alloc := alloc_arb.io.in(i).ready - trackerList(i).io.alloc_req.bits := init_arb.io.out.bits - trackerList(i).io.alloc_req.valid := init_arb.io.out.valid - - trackerList(i).io.acquire_data.bits := io.tiles(trackerList(i).io.init_client_id).acquire_data.bits.payload - trackerList(i).io.acquire_data.valid := io.tiles(trackerList(i).io.init_client_id).acquire_data.valid - trackerList(i).io.acquire_data_dep.bits := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.bits, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.bits)) - trackerList(i).io.acquire_data_dep.valid := MuxLookup(trackerList(i).io.init_client_id, acquire_data_dep_list(0).io.deq.valid, (0 until conf.ln.nClients).map( j => UFix(j) -> acquire_data_dep_list(j).io.deq.valid)) - } - for( j <- 0 until conf.ln.nClients ) { - val acquire = io.tiles(j).acquire - val acquire_data = io.tiles(j).acquire_data - val acquire_data_dep = acquire_data_dep_list(j).io.deq - init_arb.io.in(j).valid := acquire.valid - init_arb.io.in(j).bits.acquire := acquire.bits.payload - init_arb.io.in(j).bits.client_id := UFix(j) - val pop_acquires = trackerList.map(_.io.pop_acquire(j).toBool) - acquire.ready := foldR(pop_acquires)(_||_) - acquire_data_dep_list(j).io.enq.valid := acquire.ready && co.messageHasData(acquire.bits.payload) - acquire_data_dep_list(j).io.enq.bits.master_xact_id := OHToUFix(pop_acquires) - acquire_data.ready := foldR(trackerList.map(_.io.pop_acquire_data(j).toBool))(_||_) - acquire_data_dep.ready := foldR(trackerList.map(_.io.pop_acquire_dep(j).toBool))(_||_) - } - - alloc_arb.io.out.ready := init_arb.io.out.valid - - // Handle probe request generation - // Must arbitrate for each request port - val probe_arb_arr = List.fill(conf.ln.nClients)((new Arbiter(NGLOBAL_XACTS)) { new Probe() }) - for( j <- 0 until conf.ln.nClients ) { - for( i <- 0 until NGLOBAL_XACTS ) { - val t = trackerList(i).io - probe_arb_arr(j).io.in(i).bits := t.probe.bits - probe_arb_arr(j).io.in(i).valid := t.probe.valid && t.push_probe(j) - probe_cnt_inc_arr(i)(j) := probe_arb_arr(j).io.in(i).ready - } - FIFOedLogicalNetworkIOWrapper(probe_arb_arr(j).io.out) <> io.tiles(j).probe - } - -} +case class UncoreConfiguration(co: CoherencePolicyWithUncached, ln: LogicalNetworkConfiguration) abstract class CoherenceAgent(implicit conf: LogicalNetworkConfiguration) extends Component with MasterCoherenceAgent { val io = new Bundle { - val network = (new TileLinkIO).flip + val client = (new TileLinkIO).flip + val master = new UncachedTileLinkIO val incoherent = Vec(conf.nClients) { Bool() }.asInput - val mem = new ioMem } } -class L2CoherenceAgent(implicit conf: CoherenceHubConfiguration) extends CoherenceAgent()(conf.ln) +class L2CoherenceAgent(bankId: Int)(implicit conf: UncoreConfiguration) extends CoherenceAgent()(conf.ln) { implicit val lnConf = conf.ln val co = conf.co - val trackerList = new WritebackTracker(0) +: (1 to NGLOBAL_XACTS).map(new AcquireTracker(_)) + val trackerList = new WritebackTracker(0, bankId) +: (1 to NGLOBAL_XACTS).map(new AcquireTracker(_, bankId)) val release_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth must >= NPRIMARY val acquire_data_dep_q = (new Queue(NGLOBAL_XACTS)){new TrackerDependency} // depth should >= NPRIMARY - for( i <- 0 to NGLOBAL_XACTS ) { - val t = trackerList(i) - t.io.tile_incoherent := io.incoherent.toBits - t.io.mem_resp.valid := io.mem.resp.valid && (io.mem.resp.bits.tag === UFix(i)) - t.io.mem_resp.bits := io.mem.resp.bits - } - io.mem.resp.ready := trackerList.map(_.io.mem_resp.ready).reduce(_||_) + trackerList.map(_.io.tile_incoherent := io.incoherent.toBits) // Handle transaction initiation requests // Only one allocation per cycle // Init requests may or may not have data - val acquire = io.network.acquire - val acquire_data = io.network.acquire_data - val x_dep_deq = acquire_data_dep_q.io.deq + val acquire = io.client.acquire + val acquire_data = io.client.acquire_data + val acq_dep_deq = acquire_data_dep_q.io.deq val any_acquire_conflict = trackerList.map(_.io.has_acquire_conflict).reduce(_||_) val all_busy = trackerList.map(_.io.busy).reduce(_&&_) - val alloc_arb = (new Arbiter(NGLOBAL_XACTS+1)) { Bool() } - for( i <- 0 to NGLOBAL_XACTS ) { + val alloc_arb = (new Arbiter(trackerList.size)) { Bool() } + for( i <- 0 until trackerList.size ) { alloc_arb.io.in(i).valid := !trackerList(i).io.busy - trackerList(i).io.acquire.bits := acquire.bits - trackerList(i).io.acquire.valid := acquire.valid && alloc_arb.io.in(i).ready + val t = trackerList(i).io.client + t.acquire.bits := acquire.bits + t.acquire.valid := acquire.valid && alloc_arb.io.in(i).ready - trackerList(i).io.acquire_data.bits := acquire_data.bits - trackerList(i).io.acquire_data.valid := acquire_data.valid - trackerList(i).io.acquire_data_dep.bits := x_dep_deq.bits - trackerList(i).io.acquire_data_dep.valid := x_dep_deq.valid + t.acquire_data.bits := acquire_data.bits + t.acquire_data.valid := acquire_data.valid + trackerList(i).io.acquire_data_dep.bits := acq_dep_deq.bits + trackerList(i).io.acquire_data_dep.valid := acq_dep_deq.valid } - acquire.ready := trackerList.map(_.io.acquire.ready).reduce(_||_) - acquire_data.ready := trackerList.map(_.io.acquire_data.ready).reduce(_||_) + acquire.ready := trackerList.map(_.io.client.acquire.ready).reduce(_||_) + acquire_data.ready := trackerList.map(_.io.client.acquire_data.ready).reduce(_||_) acquire_data_dep_q.io.enq.valid := acquire.ready && co.messageHasData(acquire.bits.payload) - acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.acquire.ready)) - x_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_) - + acquire_data_dep_q.io.enq.bits.master_xact_id := OHToUFix(trackerList.map(_.io.client.acquire.ready)) + acq_dep_deq.ready := trackerList.map(_.io.acquire_data_dep.ready).reduce(_||_) alloc_arb.io.out.ready := acquire.valid // Handle probe request generation - val probe_arb = (new Arbiter(NGLOBAL_XACTS+1)){(new LogicalNetworkIO){ new Probe }} - for( i <- 0 to NGLOBAL_XACTS ) { - val t = trackerList(i).io - probe_arb.io.in(i).bits := t.probe.bits - probe_arb.io.in(i).valid := t.probe.valid - t.probe.ready := probe_arb.io.in(i).ready - } - io.network.probe <> probe_arb.io.out + val probe_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Probe }} + io.client.probe <> probe_arb.io.out + probe_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.probe } // Handle probe replies, which may or may not have data - val release = io.network.release - val release_data = io.network.release_data + val release = io.client.release + val release_data = io.client.release_data val voluntary = co.isVoluntary(release.bits.payload) val any_release_conflict = trackerList.tail.map(_.io.has_release_conflict).reduce(_||_) val conflict_idx = Vec(trackerList.map(_.io.has_release_conflict)){Bool()}.lastIndexWhere{b: Bool => b} val idx = Mux(voluntary, Mux(any_release_conflict, conflict_idx, UFix(0)), release.bits.payload.master_xact_id) - release.ready := trackerList.map(_.io.release.ready).reduce(_||_) - release_data.ready := trackerList.map(_.io.release_data.ready).reduce(_||_) + release.ready := trackerList.map(_.io.client.release.ready).reduce(_||_) + release_data.ready := trackerList.map(_.io.client.release_data.ready).reduce(_||_) release_data_dep_q.io.enq.valid := release.valid && co.messageHasData(release.bits.payload) release_data_dep_q.io.enq.bits.master_xact_id := idx release_data_dep_q.io.deq.ready := trackerList.map(_.io.release_data_dep.ready).reduce(_||_) - for( i <- 0 to NGLOBAL_XACTS ) { - trackerList(i).io.release_data.valid := release_data.valid - trackerList(i).io.release_data.bits := release_data.bits + for( i <- 0 until trackerList.size ) { + val t = trackerList(i).io.client + t.release.valid := release.valid && (idx === UFix(i)) + t.release.bits := release.bits + t.release_data.valid := release_data.valid + t.release_data.bits := release_data.bits trackerList(i).io.release_data_dep.valid := release_data_dep_q.io.deq.valid trackerList(i).io.release_data_dep.bits := release_data_dep_q.io.deq.bits - trackerList(i).io.release.valid := release.valid && (idx === UFix(i)) - trackerList(i).io.release.bits := release.bits } // Reply to initial requestor - // Forward memory responses from mem to tile or arbitrate to ack - val grant_arb = (new Arbiter(NGLOBAL_XACTS+1)){(new LogicalNetworkIO){ new Grant }} - for( i <- 0 to NGLOBAL_XACTS ) { - val t = trackerList(i).io - grant_arb.io.in(i).bits := t.grant.bits - grant_arb.io.in(i).valid := t.grant.valid - t.grant.ready := grant_arb.io.in(i).ready - } - io.network.grant.valid := grant_arb.io.out.valid - io.network.grant.bits := grant_arb.io.out.bits - grant_arb.io.out.ready := io.network.grant.ready - when(io.mem.resp.valid) { - io.network.grant.valid := Bool(true) - io.network.grant.bits := Vec(trackerList.map(_.io.grant.bits)){(new LogicalNetworkIO){new Grant}}(io.mem.resp.bits.tag) - for( i <- 0 to NGLOBAL_XACTS ) { - trackerList(i).io.grant.ready := (io.mem.resp.bits.tag === UFix(i)) && io.network.grant.ready - } - } + val grant_arb = (new Arbiter(trackerList.size)){(new LogicalNetworkIO){ new Grant }} + io.client.grant <> grant_arb.io.out + grant_arb.io.in zip trackerList map { case (arb, t) => arb <> t.io.client.grant } // Free finished transactions - val ack = io.network.grant_ack - for( i <- 0 to NGLOBAL_XACTS ) { - trackerList(i).io.free := ack.valid && (ack.bits.payload.master_xact_id === UFix(i)) - } + val ack = io.client.grant_ack + trackerList.map(_.io.client.grant_ack.valid := ack.valid) + trackerList.map(_.io.client.grant_ack.bits := ack.bits) ack.ready := Bool(true) // Create an arbiter for the one memory port - // We have to arbitrate between the different trackers' memory requests - // and once we have picked a request, get the right write data - val mem_req_cmd_arb = (new Arbiter(NGLOBAL_XACTS+1)) { new MemReqCmd() } - val mem_req_data_arb = (new LockingArbiter(NGLOBAL_XACTS+1)) { new MemData() } - for( i <- 0 to NGLOBAL_XACTS ) { - mem_req_cmd_arb.io.in(i) <> trackerList(i).io.mem_req_cmd - mem_req_data_arb.io.in(i) <> trackerList(i).io.mem_req_data - mem_req_data_arb.io.lock(i) <> trackerList(i).io.mem_req_lock - } - io.mem.req_cmd <> Queue(mem_req_cmd_arb.io.out) - io.mem.req_data <> Queue(mem_req_data_arb.io.out) + val outer_arb = new UncachedTileLinkIOArbiter(trackerList.size) + outer_arb.io.in zip trackerList map { case(arb, t) => arb <> t.io.master } + io.master <> outer_arb.io.out } -abstract class XactTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends Component with MemoryRequestGenerator { +abstract class XactTracker()(implicit conf: UncoreConfiguration) extends Component with OuterRequestGenerator { val co = conf.co implicit val ln = conf.ln val io = new Bundle { - val acquire = (new FIFOIO){(new LogicalNetworkIO) { new Acquire }}.flip - val acquire_data = (new FIFOIO){(new LogicalNetworkIO) { new AcquireData }}.flip - val release = (new FIFOIO){(new LogicalNetworkIO) { new Release }}.flip - val release_data = (new FIFOIO){(new LogicalNetworkIO) { new ReleaseData }}.flip - val free = Bool(INPUT) - val tile_incoherent = Bits(INPUT, conf.ln.nClients) - val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip - val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip - val mem_resp = (new FIFOIO) { new MemResp }.flip + val client = (new TileLinkIO).flip + val master = new UncachedTileLinkIO - val mem_req_cmd = (new FIFOIO) { new MemReqCmd } - val mem_req_data = (new FIFOIO) { new MemData } - val mem_req_lock = Bool(OUTPUT) - val probe = (new FIFOIO) {(new LogicalNetworkIO) { new Probe }} - val grant = (new FIFOIO) {(new LogicalNetworkIO) { new Grant }} - val busy = Bool(OUTPUT) - val has_acquire_conflict = Bool(OUTPUT) - val has_release_conflict = Bool(OUTPUT) + val tile_incoherent = Bits(INPUT, conf.ln.nClients) + val release_data_dep = (new FIFOIO) { new TrackerDependency }.flip + val acquire_data_dep = (new FIFOIO) { new TrackerDependency }.flip + + val busy = Bool(OUTPUT) + val has_acquire_conflict = Bool(OUTPUT) + val has_release_conflict = Bool(OUTPUT) } } -class WritebackTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends XactTracker(id)(conf) { +class WritebackTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfiguration) extends XactTracker()(conf) { val s_idle :: s_mem :: s_ack :: s_busy :: Nil = Enum(4){ UFix() } val state = Reg(resetVal = s_idle) val xact = Reg{ new Release } val init_client_id_ = Reg(resetVal = UFix(0, width = log2Up(conf.ln.nClients))) val release_data_needs_write = Reg(resetVal = Bool(false)) val mem_cmd_sent = Reg(resetVal = Bool(false)) + val cmd_to_write = co.getUncachedWriteAcquire(xact.addr, UFix(trackerId)) + val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId)) - io.acquire.ready := Bool(false) - io.acquire_data.ready := Bool(false) io.acquire_data_dep.ready := Bool(false) - io.mem_resp.ready := Bool(false) - io.probe.valid := Bool(false) + io.release_data_dep.ready := Bool(false) io.busy := Bool(true) io.has_acquire_conflict := Bool(false) - io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.release.bits.payload.addr) && (state != s_idle) + io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle) - io.mem_req_cmd.valid := Bool(false) - io.mem_req_cmd.bits.rw := Bool(false) - io.mem_req_cmd.bits.addr := xact.addr - io.mem_req_cmd.bits.tag := UFix(id) - io.mem_req_data.valid := Bool(false) - io.mem_req_data.bits.data := UFix(0) - io.mem_req_lock := Bool(false) - io.release.ready := Bool(false) - io.release_data.ready := Bool(false) - io.release_data_dep.ready := Bool(false) - io.grant.valid := Bool(false) - io.grant.bits.payload.g_type := co.getGrantType(xact, UFix(0)) - io.grant.bits.payload.client_xact_id := xact.client_xact_id - io.grant.bits.payload.master_xact_id := UFix(id) - io.grant.bits.header.dst := init_client_id_ + io.master.grant.ready := Bool(false) + io.master.acquire.valid := Bool(false) + io.master.acquire.bits.payload := cmd_to_write + //TODO io.master.acquire.bits.header.dst + io.master.acquire.bits.header.src := UFix(bankId) + io.master.acquire_data.valid := Bool(false) + io.master.acquire_data.bits.payload.data := UFix(0) + //TODO io.master.acquire_data.bits.header.dst + io.master.acquire_data.bits.header.src := UFix(bankId) + io.client.acquire.ready := Bool(false) + io.client.acquire_data.ready := Bool(false) + io.client.probe.valid := Bool(false) + io.client.release.ready := Bool(false) + io.client.release_data.ready := Bool(false) + io.client.grant.valid := Bool(false) + io.client.grant.bits.payload.g_type := co.getGrantType(xact, UFix(0)) + io.client.grant.bits.payload.client_xact_id := xact.client_xact_id + io.client.grant.bits.payload.master_xact_id := UFix(trackerId) + io.client.grant.bits.header.dst := init_client_id_ + io.client.grant.bits.header.src := UFix(bankId) + io.client.grant_ack.valid := Bool(false) switch (state) { is(s_idle) { - when( io.release.valid ) { - xact := io.release.bits.payload - init_client_id_ := io.release.bits.header.src - release_data_needs_write := co.messageHasData(io.release.bits.payload) + when( io.client.release.valid ) { + xact := io.client.release.bits.payload + init_client_id_ := io.client.release.bits.header.src + release_data_needs_write := co.messageHasData(io.client.release.bits.payload) mem_cnt := UFix(0) mem_cmd_sent := Bool(false) - io.release.ready := Bool(true) + io.client.release.ready := Bool(true) state := s_mem } } is(s_mem) { when (release_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.release_data, + doOuterReqWrite(io.master.acquire, + io.master.acquire_data, + io.client.release_data, release_data_needs_write, mem_cmd_sent, io.release_data_dep.ready, - io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id))) + io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(trackerId))) } . otherwise { state := s_ack } } is(s_ack) { - io.grant.valid := Bool(true) - when(io.grant.ready) { state := s_idle } + io.client.grant.valid := Bool(true) + when(io.client.grant.ready) { state := s_idle } } } } -class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends XactTracker(id)(conf) { +class AcquireTracker(trackerId: Int, bankId: Int)(implicit conf: UncoreConfiguration) extends XactTracker()(conf) { val s_idle :: s_ack :: s_mem :: s_probe :: s_busy :: Nil = Enum(5){ UFix() } val state = Reg(resetVal = s_idle) val xact = Reg{ new Acquire } @@ -697,63 +208,65 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends val x_needs_read = Reg(resetVal = Bool(false)) val acquire_data_needs_write = Reg(resetVal = Bool(false)) val release_data_needs_write = Reg(resetVal = Bool(false)) - val x_w_mem_cmd_sent = Reg(resetVal = Bool(false)) - val p_w_mem_cmd_sent = Reg(resetVal = Bool(false)) + val cmd_to_write = co.getUncachedWriteAcquire(xact.addr, UFix(trackerId)) + val cmd_to_read = co.getUncachedReadAcquire(xact.addr, UFix(trackerId)) + val a_w_mem_cmd_sent = Reg(resetVal = Bool(false)) + val r_w_mem_cmd_sent = Reg(resetVal = Bool(false)) val probe_initial_flags = Bits(width = conf.ln.nClients) probe_initial_flags := Bits(0) if (conf.ln.nClients > 1) { // issue self-probes for uncached read xacts to facilitate I$ coherence - // TODO: this is hackish; figure out how to do it more systematically - val probe_self = co match { - case u: CoherencePolicyWithUncached => u.isUncachedReadTransaction(io.acquire.bits.payload) - case _ => Bool(false) - } - val myflag = Mux(probe_self, Bits(0), UFixToOH(io.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0))) + val probe_self = co.needsSelfProbe(io.client.acquire.bits.payload) + val myflag = Mux(probe_self, Bits(0), UFixToOH(io.client.acquire.bits.header.src(log2Up(conf.ln.nClients)-1,0))) probe_initial_flags := ~(io.tile_incoherent | myflag) } io.busy := state != s_idle - io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.acquire.bits.payload.addr) && (state != s_idle) - io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.release.bits.payload.addr) && (state != s_idle) - io.mem_req_cmd.valid := Bool(false) - io.mem_req_cmd.bits.rw := Bool(false) - io.mem_req_cmd.bits.addr := xact.addr - io.mem_req_cmd.bits.tag := UFix(id) - io.mem_req_data.valid := Bool(false) - io.mem_req_data.bits.data := UFix(0) - io.mem_req_lock := Bool(false) - io.probe.valid := Bool(false) - io.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0)) - io.probe.bits.payload.master_xact_id := UFix(id) - io.probe.bits.payload.addr := xact.addr - io.probe.bits.header.dst := UFix(0) - io.grant.bits.payload.data := io.mem_resp.bits.data - io.grant.bits.payload.g_type := grant_type - io.grant.bits.payload.client_xact_id := xact.client_xact_id - io.grant.bits.payload.master_xact_id := UFix(id) - io.grant.bits.header.dst := init_client_id_ - io.grant.valid := (io.mem_resp.valid && (UFix(id) === io.mem_resp.bits.tag)) - io.acquire.ready := Bool(false) - io.acquire_data.ready := Bool(false) + io.has_acquire_conflict := co.isCoherenceConflict(xact.addr, io.client.acquire.bits.payload.addr) && (state != s_idle) + io.has_release_conflict := co.isCoherenceConflict(xact.addr, io.client.release.bits.payload.addr) && (state != s_idle) + io.master.acquire.valid := Bool(false) + io.master.acquire.bits.payload := co.getUncachedReadAcquire(xact.addr, UFix(trackerId)) + //TODO io.master.acquire.bits.header.dst + io.master.acquire.bits.header.src := UFix(bankId) + io.master.acquire_data.valid := Bool(false) + io.master.acquire_data.bits.payload.data := UFix(0) + //TODO io.master.acquire_data.bits.header.dst + io.master.acquire_data.bits.header := UFix(bankId) + io.client.probe.valid := Bool(false) + io.client.probe.bits.payload.p_type := co.getProbeType(xact.a_type, UFix(0)) + io.client.probe.bits.payload.master_xact_id := UFix(trackerId) + io.client.probe.bits.payload.addr := xact.addr + io.client.probe.bits.header.dst := UFix(0) + io.client.probe.bits.header.src := UFix(bankId) + io.client.grant.bits.payload.data := io.master.grant.bits.payload.data + io.client.grant.bits.payload.g_type := grant_type + io.client.grant.bits.payload.client_xact_id := xact.client_xact_id + io.client.grant.bits.payload.master_xact_id := UFix(trackerId) + io.client.grant.bits.header.dst := init_client_id_ + io.client.grant.bits.header.src := UFix(bankId) + io.client.grant.valid := (io.master.grant.valid && (UFix(trackerId) === io.master.grant.bits.payload.client_xact_id)) + io.client.acquire.ready := Bool(false) + io.client.acquire_data.ready := Bool(false) io.acquire_data_dep.ready := Bool(false) - io.release.ready := Bool(false) - io.release_data.ready := Bool(false) + io.client.release.ready := Bool(false) + io.client.release_data.ready := Bool(false) io.release_data_dep.ready := Bool(false) - io.mem_resp.ready := io.grant.ready + io.master.grant.ready := io.client.grant.ready + io.client.grant_ack.valid := Bool(false) switch (state) { is(s_idle) { - when( io.acquire.valid ) { - xact := io.acquire.bits.payload - init_client_id_ := io.acquire.bits.header.src + when( io.client.acquire.valid ) { + xact := io.client.acquire.bits.payload + init_client_id_ := io.client.acquire.bits.header.src init_sharer_cnt_ := UFix(conf.ln.nClients) // TODO: Broadcast only - acquire_data_needs_write := co.messageHasData(io.acquire.bits.payload) - x_needs_read := co.needsMemRead(io.acquire.bits.payload.a_type, UFix(0)) + acquire_data_needs_write := co.messageHasData(io.client.acquire.bits.payload) + x_needs_read := co.needsOuterRead(io.client.acquire.bits.payload.a_type, UFix(0)) probe_flags := probe_initial_flags mem_cnt := UFix(0) - p_w_mem_cmd_sent := Bool(false) - x_w_mem_cmd_sent := Bool(false) - io.acquire.ready := Bool(true) + r_w_mem_cmd_sent := Bool(false) + a_w_mem_cmd_sent := Bool(false) + io.client.acquire.ready := Bool(true) if(conf.ln.nClients > 1) { release_count := PopCount(probe_initial_flags) state := Mux(probe_initial_flags.orR, s_probe, s_mem) @@ -763,78 +276,76 @@ class AcquireTracker(id: Int)(implicit conf: CoherenceHubConfiguration) extends is(s_probe) { val curr_p_id = PriorityEncoder(probe_flags) when(probe_flags.orR) { - io.probe.valid := Bool(true) - io.probe.bits.header.dst := curr_p_id + io.client.probe.valid := Bool(true) + io.client.probe.bits.header.dst := curr_p_id } - when(io.probe.ready) { + when(io.client.probe.ready) { probe_flags := probe_flags & ~(UFixToOH(curr_p_id)) } - when(io.release.valid) { - io.release.ready := Bool(true) + when(io.client.release.valid) { + io.client.release.ready := Bool(true) if(conf.ln.nClients > 1) release_count := release_count - UFix(1) when(release_count === UFix(1)) { state := s_mem } - release_data_needs_write := co.messageHasData(io.release.bits.payload) + release_data_needs_write := co.messageHasData(io.client.release.bits.payload) } } is(s_mem) { when (release_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.release_data, + doOuterReqWrite(io.master.acquire, + io.master.acquire_data, + io.client.release_data, release_data_needs_write, - p_w_mem_cmd_sent, + r_w_mem_cmd_sent, io.release_data_dep.ready, - io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(id))) + io.release_data_dep.valid && (io.release_data_dep.bits.master_xact_id === UFix(trackerId))) } . elsewhen(acquire_data_needs_write) { - doMemReqWrite(io.mem_req_cmd, - io.mem_req_data, - io.mem_req_lock, - io.acquire_data, + doOuterReqWrite(io.master.acquire, + io.master.acquire_data, + io.client.acquire_data, acquire_data_needs_write, - x_w_mem_cmd_sent, + a_w_mem_cmd_sent, io.acquire_data_dep.ready, - io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(id))) + io.acquire_data_dep.valid && (io.acquire_data_dep.bits.master_xact_id === UFix(trackerId))) } . elsewhen (x_needs_read) { - doMemReqRead(io.mem_req_cmd, x_needs_read) + doOuterReqRead(io.master.acquire, x_needs_read) } . otherwise { state := Mux(co.needsAckReply(xact.a_type, UFix(0)), s_ack, - Mux(co.requiresAck(io.grant.bits.payload), s_busy, s_idle)) + Mux(co.requiresAck(io.client.grant.bits.payload), s_busy, s_idle)) } } is(s_ack) { - io.grant.valid := Bool(true) - when(io.grant.ready) { state := Mux(co.requiresAck(io.grant.bits.payload), s_busy, s_idle) } + io.client.grant.valid := Bool(true) + when(io.client.grant.ready) { state := Mux(co.requiresAck(io.client.grant.bits.payload), s_busy, s_idle) } } is(s_busy) { // Nothing left to do but wait for transaction to complete - when (io.free) { + when (io.client.grant_ack.valid && io.client.grant_ack.bits.payload.master_xact_id === UFix(trackerId)) { state := s_idle } } } } -trait MemoryRequestGenerator { +abstract trait OuterRequestGenerator { + val cmd_to_write: Acquire + val cmd_to_read: Acquire val mem_cnt = Reg(resetVal = UFix(0, width = log2Up(REFILL_CYCLES))) val mem_cnt_next = mem_cnt + UFix(1) - val mem_cnt_max = ~UFix(0, width = log2Up(REFILL_CYCLES)) - def doMemReqWrite[T <: Data](req_cmd: FIFOIO[MemReqCmd], req_data: FIFOIO[MemData], lock: Bool, data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) { - req_cmd.bits.rw := Bool(true) - req_data.bits := data.bits.payload - when(req_cmd.ready && req_cmd.valid) { + def doOuterReqWrite[T <: Data](master_acq: FIFOIO[LogicalNetworkIO[Acquire]], master_acq_data: FIFOIO[LogicalNetworkIO[AcquireData]], client_data: FIFOIO[LogicalNetworkIO[T]], trigger: Bool, cmd_sent: Bool, pop_dep: Bool, at_front_of_dep_queue: Bool) { + master_acq.bits.payload := cmd_to_write + master_acq_data.bits.payload := client_data.bits.payload + when(master_acq.ready && master_acq.valid) { cmd_sent := Bool(true) } when (at_front_of_dep_queue) { - req_cmd.valid := !cmd_sent && req_data.ready && data.valid - lock := data.valid || cmd_sent - when (req_cmd.ready || cmd_sent) { - req_data.valid := data.valid - when(req_data.ready) { - data.ready:= Bool(true) - when (data.valid) { + master_acq.valid := !cmd_sent && master_acq_data.ready && client_data.valid + when (master_acq.ready || cmd_sent) { + master_acq_data.valid := client_data.valid + when(master_acq_data.ready) { + client_data.ready:= Bool(true) + when (client_data.valid) { mem_cnt := mem_cnt_next when(mem_cnt === UFix(REFILL_CYCLES-1)) { pop_dep := Bool(true) @@ -846,10 +357,10 @@ trait MemoryRequestGenerator { } } - def doMemReqRead(req_cmd: FIFOIO[MemReqCmd], trigger: Bool) { - req_cmd.valid := Bool(true) - req_cmd.bits.rw := Bool(false) - when(req_cmd.ready) { + def doOuterReqRead(master_acq: FIFOIO[LogicalNetworkIO[Acquire]], trigger: Bool) { + master_acq.valid := Bool(true) + master_acq.bits.payload := cmd_to_read + when(master_acq.ready) { trigger := Bool(false) } }