tilelink2 Monitor: use Parameters instead of global variables

src/main/scala/rocketchip/BaseTop.scala

@@ -12,9 +12,6 @@ import uncore.devices._
 import util._
 import rocket._
 
-/** Enable or disable monitoring of Diplomatic buses */
-case object TLEmitMonitors extends Field[Boolean]
-
 abstract class BareTop(implicit p: Parameters) extends LazyModule {
   TopModule.contents = Some(this)
 }
@@ -33,8 +30,6 @@ abstract class BareTopModule[+L <: BareTop, +B <: BareTopBundle[L]](_outer: L, _
 trait TopNetwork extends HasPeripheryParameters {
   val module: TopNetworkModule
 
-  TLImp.emitMonitors = p(TLEmitMonitors)
-
   // Add a SoC and peripheral bus
   val socBus = LazyModule(new TLXbar)
   val peripheryBus = LazyModule(new TLXbar)

src/main/scala/rocketchip/Configs.scala

@@ -8,7 +8,7 @@ import junctions._
 import rocket._
 import diplomacy._
 import uncore.agents._
-import uncore.tilelink._
+import uncore.tilelink2._
 import uncore.devices._
 import uncore.converters._
 import util._
@@ -21,8 +21,11 @@ import config._
 
 class BasePlatformConfig extends Config(
   (pname,site,here) => pname match {
+    // TileLink connection parameters
+    case TLMonitorBuilder => (args: TLMonitorArgs) => Some(LazyModule(new TLMonitor(args)))
+    case TLFuzzReadyValid => false
+    case TLCombinationalCheck => false
     //Memory Parameters
-    case TLEmitMonitors => true
     case NExtTopInterrupts => 2
     case SOCBusConfig => site(L1toL2Config)
     case PeripheryBusConfig => TLBusConfig(beatBytes = 4)
@@ -143,16 +146,9 @@ class With64BitPeriphery extends Config (
   }
 )
 
-class WithTLMonitors extends Config (
-  (pname, site, here) => pname match {
-    case TLEmitMonitors => true
-    case _ => throw new CDEMatchError
-  }
-)
-
 class WithoutTLMonitors extends Config (
   (pname, site, here) => pname match {
-    case TLEmitMonitors => false
+    case TLMonitorBuilder => (args: TLMonitorArgs) => None
     case _ => throw new CDEMatchError
   }
 )

src/main/scala/uncore/tilelink2/Monitor.scala

@@ -7,7 +7,24 @@ import chisel3.internal.sourceinfo.{SourceInfo, SourceLine}
 import config._
 import diplomacy._
 
-class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo)(implicit p: Parameters) extends LazyModule
+case class TLMonitorArgs(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: SourceInfo, p: Parameters)
+
+abstract class TLMonitorBase(args: TLMonitorArgs) extends LazyModule()(args.p)
+{
+  implicit val sourceInfo = args.sourceInfo
+
+  def legalize(bundle: TLBundleSnoop, edge: TLEdge): Unit
+
+  lazy val module = new LazyModuleImp(this) {
+    val io = new Bundle {
+      val in = args.gen().asInput
+    }
+
+    legalize(io.in, args.edge())
+  }
+}
+
+class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
 {
   def extra(implicit sourceInfo: SourceInfo) = {
     sourceInfo match {
@@ -410,17 +427,9 @@ class TLMonitor(gen: () => TLBundleSnoop, edge: () => TLEdge, sourceInfo: Source
     inflight := (inflight | a_set) & ~d_clr
   }
 
-  def legalize(bundle: TLBundleSnoop, edge: TLEdge)(implicit sourceInfo: SourceInfo) {
+  def legalize(bundle: TLBundleSnoop, edge: TLEdge) {
     legalizeFormat      (bundle, edge)
     legalizeMultibeat   (bundle, edge)
     legalizeSourceUnique(bundle, edge)
   }
-
-  lazy val module = new LazyModuleImp(this) {
-    val io = new Bundle {
-      val in = gen().asInput
-    }
-
-    legalize(io.in, edge())(sourceInfo)
-  }
 }

src/main/scala/uncore/tilelink2/Nodes.scala

@@ -8,6 +8,10 @@ import config._
 import diplomacy._
 import scala.collection.mutable.ListBuffer
 
+case object TLMonitorBuilder extends Field[TLMonitorArgs => Option[TLMonitorBase]]
+case object TLFuzzReadyValid extends Field[Boolean]
+case object TLCombinationalCheck extends Field[Boolean]
+
 object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TLEdgeOut, TLEdgeIn, TLBundle]
 {
   def edgeO(pd: TLClientPortParameters, pu: TLManagerPortParameters): TLEdgeOut = new TLEdgeOut(pd, pu)
@@ -21,24 +25,16 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
     Vec(ei.size, TLBundle(ei.map(_.bundle).reduce(_.union(_))))
   }
 
-  var emitMonitors = true
-  var stressTestDecoupled = false
-  var combinationalCheck = false
-
   def colour = "#000000" // black
   override def labelI(ei: TLEdgeIn)  = (ei.manager.beatBytes * 8).toString
   override def labelO(eo: TLEdgeOut) = (eo.manager.beatBytes * 8).toString
 
   def connect(bo: => TLBundle, bi: => TLBundle, ei: => TLEdgeIn)(implicit p: Parameters, sourceInfo: SourceInfo): (Option[LazyModule], () => Unit) = {
-    val monitor = if (emitMonitors) {
+    val monitor = p(TLMonitorBuilder)(TLMonitorArgs(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo, p))
-      Some(LazyModule(new TLMonitor(() => new TLBundleSnoop(bo.params), () => ei, sourceInfo)))
-    } else {
-      None
-    }
     (monitor, () => {
       bi <> bo
       monitor.foreach { _.module.io.in := TLBundleSnoop(bo) }
-      if (combinationalCheck) {
+      if (p(TLCombinationalCheck)) {
         // It is forbidden for valid to depend on ready in TL2
         // If someone did that, then this will create a detectable combinational loop
         bo.a.ready := bi.a.ready && bo.a.valid
@@ -47,7 +43,7 @@ object TLImp extends NodeImp[TLClientPortParameters, TLManagerPortParameters, TL
         bi.d.ready := bo.d.ready && bi.d.valid
         bo.e.ready := bi.e.ready && bo.e.valid
       }
-      if (stressTestDecoupled) {
+      if (p(TLCombinationalCheck)) {
         // Randomly stall the transfers
         val allow = LFSRNoiseMaker(5)
         bi.a.valid := bo.a.valid && allow(0)