riscv/rocket-chip
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cleanup, fixes, initial commit for dtlb.scala

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This commit is contained in:
Rimas Avizienis
2011-11-09 21:54:11 -08:00
parent e96430d862
commit c29d2821b4
8 changed files with 230 additions and 33 deletions
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40
rocket/src/main/scala/itlb.scala
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@ -52,7 +52,7 @@ class ioTLB_PTW extends Bundle
}
// interface between ITLB and fetch stage of pipeline
class ioITLB_CPU extends Bundle
class ioITLB_CPU(view: List[String] = null) extends Bundle(view)
{
// status bits (from PCR), to check current permission and whether VM is enabled
val status = Bits(17, 'input);
@ -62,10 +62,12 @@ class ioITLB_CPU extends Bundle
val req_val = Bool('input);
val req_rdy = Bool('output);
val req_asid = Bits(ASID_BITS, 'input);
val req_vpn = Bits(VPN_BITS, 'input);
// val req_vpn = Bits(VPN_BITS, 'input);
val req_addr = UFix(VADDR_BITS, 'input);
// lookup responses
val resp_val = Bool('output);
val resp_ppn = Bits(PPN_BITS, 'output);
// val resp_ppn = Bits(PPN_BITS, 'output);
val resp_addr = UFix(PADDR_BITS, 'output);
val exception = Bool('output);
}
@ -85,7 +87,9 @@ class rocketITLB(entries: Int) extends Component
val tag_cam = new rocketCAM(entries, addr_bits, ASID_BITS+VPN_BITS);
val lookup_tag = Cat(io.cpu.req_asid, io.cpu.req_vpn);
val req_vpn = io.cpu.req_addr(VADDR_BITS-1,PGIDX_BITS);
val req_idx = io.cpu.req_addr(PGIDX_BITS-1,0);
val lookup_tag = Cat(io.cpu.req_asid, req_vpn);
val r_refill_tag = Reg(resetVal = Bits(0, ASID_BITS+VPN_BITS));
val r_refill_waddr = Reg(resetVal = UFix(0, addr_bits));
val repl_count = Reg(resetVal = UFix(0, addr_bits));
@ -99,12 +103,12 @@ class rocketITLB(entries: Int) extends Component
val tag_hit_addr = tag_cam.io.hit_addr;
// extract fields from status register
val status_mode = io.cpu.status(6).toBool;
val status_vm = io.cpu.status(16).toBool
val status_mode = io.cpu.status(6).toBool; // user/supervisor mode
val status_vm = io.cpu.status(16).toBool // virtual memory enable
// extract fields from PT permission bits
val ptw_perm_ux = io.ptw.resp_perm(4);
val ptw_perm_sx = io.ptw.resp_perm(7);
val ptw_perm_ux = io.ptw.resp_perm(0);
val ptw_perm_sx = io.ptw.resp_perm(3);
// valid bit array
val vb_array = Reg(resetVal = Bits(0, entries));
@ -120,7 +124,14 @@ class rocketITLB(entries: Int) extends Component
val sx_array = Reg(resetVal = Bits(0, entries)); // supervisor execute permission
when (io.ptw.resp_val) {
ux_array <== ux_array.bitSet(r_refill_waddr, ptw_perm_ux);
sx_array <== ux_array.bitSet(r_refill_waddr, ptw_perm_sx);
sx_array <== sx_array.bitSet(r_refill_waddr, ptw_perm_sx);
}
// when the page table lookup reports an error, set both execute permission
// bits to 0 so the next access will cause an exceptions
when (io.ptw.resp_err) {
ux_array <== ux_array.bitSet(r_refill_waddr, Bool(false));
sx_array <== sx_array.bitSet(r_refill_waddr, Bool(false));
}
// high if there are any unused (invalid) entries in the ITLB
@ -150,11 +161,14 @@ class rocketITLB(entries: Int) extends Component
io.cpu.req_rdy := (state === s_ready);
io.cpu.resp_val := Mux(status_vm, tag_hit, io.cpu.req_val);
io.cpu.resp_ppn := Mux(status_vm, io.cpu.req_vpn(PPN_BITS-1, 0), tag_ram(tag_hit_addr));
io.cpu.exception := itlb_exception;
// io.cpu.resp_ppn := Mux(status_vm, io.cpu.req_vpn(PPN_BITS-1, 0), tag_ram(tag_hit_addr));
io.cpu.resp_addr :=
Mux(status_vm, Cat(tag_ram(tag_hit_addr), req_idx),
io.cpu.req_addr(PADDR_BITS-1,0)).toUFix;
io.cpu.exception := status_vm && itlb_exception;
io.ptw.req_val := (state === s_request);
io.ptw.req_vpn := r_refill_tag;
io.ptw.req_vpn := r_refill_tag(VPN_BITS-1,0);
// control state machine
switch (state) {
@ -169,7 +183,7 @@ class rocketITLB(entries: Int) extends Component
}
}
is (s_wait) {
when (io.ptw.resp_val) {
when (io.ptw.resp_val || io.ptw.resp_err) {
state <== s_ready;
}
}