riscv/rocket-chip
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cleanup, fixes, initial commit for dtlb.scala

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Rimas Avizienis
2011-11-09 21:54:11 -08:00
parent e96430d862
commit c29d2821b4
8 changed files with 230 additions and 33 deletions
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4
rocket/src/main/scala/icache.scala
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@ -5,10 +5,10 @@ import Node._;
import Constants._;
import scala.math._;
// interface between I$ and processor (32 bits wide)
// interface between I$ and pipeline/ITLB (32 bits wide)
class ioImem(view: List[String] = null) extends Bundle (view)
{
val req_addr = UFix(32, 'input);
val req_addr = UFix(PADDR_BITS, 'input);
val req_val = Bool('input);
val req_rdy = Bool('output);
val resp_data = Bits(32, 'output);