cleanup, fixes, initial commit for dtlb.scala
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@ -4,7 +4,7 @@ import Chisel._;
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import Node._;
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import Constants._;
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class ioDebug extends Bundle()
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class ioDebug(view: List[String] = null) extends Bundle(view)
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{
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val error_mode = Bool('output);
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val log_control = Bool('output);
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@ -66,13 +66,14 @@ class rocketProc extends Component
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ctrl.io.imem.req_rdy := itlb.io.cpu.req_rdy && io.imem.req_rdy;
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itlb.io.cpu.req_asid := Bits(0,ASID_BITS); // FIXME: connect to PCR
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itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
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// itlb.io.cpu.req_vpn := dpath.io.imem.req_addr(VADDR_BITS-1,PGIDX_BITS);
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itlb.io.cpu.req_addr := dpath.io.imem.req_addr;
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io.imem.req_val := itlb.io.cpu.resp_val;
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io.imem.req_addr := Cat(itlb.io.cpu.resp_ppn, dpath.io.imem.req_addr(PGIDX_BITS-1,0)).toUFix;
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io.imem.req_addr := itlb.io.cpu.resp_addr;
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ctrl.io.imem.resp_val := io.imem.resp_val;
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dpath.io.itlb_xcpt := itlb.io.cpu.exception;
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ctrl.io.itlb_xcpt := itlb.io.cpu.exception;
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ptw.io.itlb <> itlb.io.ptw;
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ptw.io.ptbr := dpath.io.ptbr;
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