riscv/rocket-chip
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Fix an overly strict D$ assertion

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This commit is contained in:
Andrew Waterman 2016-10-06 15:52:21 -07:00
parent fe641c14a1
commit c22438b822
1 changed files with 3 additions and 2 deletions
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5
src/main/scala/rocket/dcache.scala
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@ -325,8 +325,9 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
when (io.mem.grant.fire() && refillDone) { cached_grant_wait := false }
// data refill
dataArb.io.in(1).valid := grantIsRefill && io.mem.grant.valid
assert(dataArb.io.in(1).ready || !dataArb.io.in(1).valid)
val doRefillBeat = grantIsRefill && io.mem.grant.valid
dataArb.io.in(1).valid := doRefillBeat
assert(dataArb.io.in(1).ready || !doRefillBeat)
dataArb.io.in(1).bits.write := true
dataArb.io.in(1).bits.addr := Cat(s2_req.addr(paddrBits-1, blockOffBits), io.mem.grant.bits.addr_beat) << beatOffBits
dataArb.io.in(1).bits.way_en := s2_victim_way