Fix an overly strict D$ assertion
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@ -325,8 +325,9 @@ class DCache(implicit p: Parameters) extends L1HellaCacheModule()(p) {
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when (io.mem.grant.fire() && refillDone) { cached_grant_wait := false }
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// data refill
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dataArb.io.in(1).valid := grantIsRefill && io.mem.grant.valid
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assert(dataArb.io.in(1).ready || !dataArb.io.in(1).valid)
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val doRefillBeat = grantIsRefill && io.mem.grant.valid
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dataArb.io.in(1).valid := doRefillBeat
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assert(dataArb.io.in(1).ready || !doRefillBeat)
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dataArb.io.in(1).bits.write := true
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dataArb.io.in(1).bits.addr := Cat(s2_req.addr(paddrBits-1, blockOffBits), io.mem.grant.bits.addr_beat) << beatOffBits
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dataArb.io.in(1).bits.way_en := s2_victim_way
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