tilelink2: Rename GPIO to Example to avoid conflicts with real GPIO devices

src/main/scala/uncore/tilelink2/Example.scala

@@ -0,0 +1,29 @@
+// See LICENSE for license details.
+
+package uncore.tilelink2
+
+import Chisel._
+
+case class ExampleParams(num: Int, address: BigInt)
+
+trait ExampleBundle
+{
+  val params: ExampleParams
+  val gpio = UInt(width = params.num)
+}
+
+trait ExampleModule extends HasRegMap
+{
+  val params: ExampleParams
+  val io: ExampleBundle
+
+  val state = RegInit(UInt(0))
+  io.gpio := state
+
+  regmap(0 -> Seq(RegField(params.num, state)))
+}
+
+// Create a concrete TL2 version of the abstract Example slave
+class TLExample(p: ExampleParams) extends TLRegisterRouter(p.address)(
+  new TLRegBundle(p, _)    with ExampleBundle)(
+  new TLRegModule(p, _, _) with ExampleModule)

src/main/scala/uncore/tilelink2/GPIO.scala

@@ -1,29 +0,0 @@
-// See LICENSE for license details.
-
-package uncore.tilelink2
-
-import Chisel._
-
-case class GPIOParams(num: Int, address: BigInt)
-
-trait GPIOBundle
-{
-  val params: GPIOParams
-  val gpio = UInt(width = params.num)
-}
-
-trait GPIOModule extends HasRegMap
-{
-  val params: GPIOParams
-  val io: GPIOBundle
-
-  val state = RegInit(UInt(0))
-  io.gpio := state
-
-  regmap(0 -> Seq(RegField(params.num, state)))
-}
-
-// Create a concrete TL2 version of the abstract GPIO slave
-class TLGPIO(p: GPIOParams) extends TLRegisterRouter(p.address)(
-  new TLRegBundle(p, _)    with GPIOBundle)(
-  new TLRegModule(p, _, _) with GPIOModule)