From c1b7c84f090cef1d3c8ccc9c5a935a1b8318d227 Mon Sep 17 00:00:00 2001
From: Henry Cook <henry@sifive.com>
Date: Wed, 18 Jan 2017 18:15:24 -0800
Subject: [PATCH] [rocket] bugfix: RoccExampleConfig looks up PAddrBits too
 early

---
 src/main/scala/rocket/Rocc.scala | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/main/scala/rocket/Rocc.scala b/src/main/scala/rocket/Rocc.scala
index 1fae2f7a..db09f909 100644
--- a/src/main/scala/rocket/Rocc.scala
+++ b/src/main/scala/rocket/Rocc.scala
@@ -75,7 +75,7 @@ trait CanHaveLegacyRoccsModule extends CanHaveSharedFPUModule with CanHavePTWMod
 
 }
 
-class LegacyRoccComplex(implicit p: Parameters) extends LazyModule with HasCoreParameters {
+class LegacyRoccComplex(implicit p: Parameters) extends LazyModule {
   val buildRocc = p(BuildRoCC)
   val usingRocc = !buildRocc.isEmpty
   val nRocc = buildRocc.size
@@ -84,11 +84,11 @@ class LegacyRoccComplex(implicit p: Parameters) extends LazyModule with HasCoreP
   val nPTWPorts = buildRocc.map(_.nPTWPorts).sum
   val roccOpcodes = buildRocc.map(_.opcodes)
 
-  val legacies = List.fill(nMemChannels) { LazyModule(new TLLegacy) }
+  val legacies = List.fill(nMemChannels) { LazyModule(new TLLegacy()(p.alterPartial({ case PAddrBits => 32 }))) }
   val masterNodes = legacies.map(_ => TLOutputNode())
   legacies.zip(masterNodes).foreach { case(l,m) => m := TLHintHandler()(l.node) }
 
-  lazy val module = new LazyModuleImp(this) {
+  lazy val module = new LazyModuleImp(this) with HasCoreParameters {
     val io = new Bundle {
       val tl = masterNodes.map(_.bundleOut)
       val dcache = Vec(nRocc, new HellaCacheIO)
@@ -117,7 +117,7 @@ class LegacyRoccComplex(implicit p: Parameters) extends LazyModule with HasCoreP
         case RoccNMemChannels => accelParams.nMemChannels
         case RoccNPTWPorts => accelParams.nPTWPorts
       }))
-      val dcIF = Module(new SimpleHellaCacheIF)
+      val dcIF = Module(new SimpleHellaCacheIF()(p.alterPartial({ case CacheName => CacheName("L1D") })))
       rocc.io.cmd <> cmdRouter.io.out(i)
       rocc.io.exception := io.core.exception
       dcIF.io.requestor <> rocc.io.mem
@@ -127,7 +127,7 @@ class LegacyRoccComplex(implicit p: Parameters) extends LazyModule with HasCoreP
       rocc
     }
 
-    (nRocc to legacies.size) zip roccs.map(_.io.utl) foreach { case(i, utl) =>
+    (nRocc until legacies.size) zip roccs.map(_.io.utl) foreach { case(i, utl) =>
       legacies(i).module.io.legacy <> utl
     }
     io.core.busy := cmdRouter.io.busy || roccs.map(_.io.busy).reduce(_ || _)