tilelink2 SourceShrinker: a concurrency reducing adapter

2016-11-22 21:20:26 -08:00
parent 0097274ea3
commit c0b27999ea
3 changed files with 80 additions and 1 deletions
--- a/src/main/scala/uncore/tilelink2/SRAM.scala
+++ b/src/main/scala/uncore/tilelink2/SRAM.scala
@ -72,7 +72,6 @@ class TLRAM(address: AddressSet, executable: Boolean = true, beatBytes: Int = 4)
      mem.write(memAddress, wdata, in.a.bits.mask.toBools)
    }
    val ren = in.a.fire() && read
-    def holdUnless[T <: Data](in : T, enable: Bool): T = Mux(!enable, RegEnable(in, enable), in)
    rdata := holdUnless(mem.read(memAddress, ren), RegNext(ren))

    // Tie off unused channels