From c09eeb7fd2f6b67e896a80dbedefc733fd68716e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Wed, 7 Mar 2012 01:42:08 -0800 Subject: [PATCH] fix D$ next-state logic it was using the CPU command from the wrong pipeline stage, which was a don't-care with ThreeStateIncoherence. --- rocket/src/main/scala/nbdcache.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 54615a74..6dc262a5 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -764,7 +764,7 @@ class HellaCacheUniproc extends HellaCache with FourStateCoherence { meta_arb.io.in(2).bits.way_en := ~UFix(0, NWAYS) val early_tag_nack = !meta_arb.io.in(2).ready val cpu_req_tag = Cat(io.cpu.req_ppn, r_cpu_req_idx)(tagmsb,taglsb) - val tag_match_arr = (0 until NWAYS).map( w => isHit(io.cpu.req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) + val tag_match_arr = (0 until NWAYS).map( w => isHit(r_cpu_req_cmd, meta.io.resp(w).state) && (meta.io.resp(w).tag === cpu_req_tag)) val tag_match = Cat(Bits(0),tag_match_arr:_*).orR val tag_hit = r_cpu_req_val && tag_match val tag_miss = r_cpu_req_val && !tag_match