diff --git a/Makefrag b/Makefrag
index f1ebd7a4..33cd334e 100644
--- a/Makefrag
+++ b/Makefrag
@@ -14,7 +14,7 @@ SBT := CHISEL_SUBMODULE="chisel$(CHISEL_VERSION)" java -Xmx2048M -Xss8M -XX:MaxP
 SHELL := /bin/bash
 
 ifeq ($(CHISEL_VERSION),2)
-CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) $(CHISEL_VERSION) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
+CHISEL_ARGS := $(PROJECT) $(MODEL) $(CONFIG) --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
 else
 CHISEL_ARGS := --W0W --minimumCompatibility 3.0.0 --backend $(BACKEND) --configName $(CONFIG) --compileInitializationUnoptimized --targetDir $(generated_dir)
 endif
diff --git a/src/main/scala/TestBench.scala b/src/main/scala/TestBench.scala
index 61a38097..cf22582c 100644
--- a/src/main/scala/TestBench.scala
+++ b/src/main/scala/TestBench.scala
@@ -7,11 +7,7 @@ import Chisel._
 object TestBenchGeneration extends FileSystemUtilities {
   def generateVerilogFragment(
     topModuleName: String, configClassName: String,
-    nMemChannel: Int, chiselVersion: Int) = {
-
-    // Chisel 3 uses $ during name expansion whereas Chisel 2 uses _
-    require(chiselVersion == 2 || chiselVersion == 3)
-    val delim = if (chiselVersion == 3) "$" else "_"
+    nMemChannel: Int) = {
 
     // YUNSUP:
     // I originally wrote this using a 2d wire array, but of course Synopsys'
@@ -167,54 +163,54 @@ object TestBenchGeneration extends FileSystemUtilities {
 """ } mkString
 
     val nasti_connections = (0 until nMemChannel) map { i => s"""
-    .io${delim}mem${delim}${i}${delim}ar${delim}valid (ar_valid_delay_$i),
-    .io${delim}mem${delim}${i}${delim}ar${delim}ready (ar_ready_delay_$i),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}addr (ar_addr_delay_$i),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}id (ar_id_delay_$i),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}size (ar_size_delay_$i),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}len (ar_len_delay_$i),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}burst (),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}lock (),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}cache (),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}prot (),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}qos (),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}region (),
-    .io${delim}mem${delim}${i}${delim}ar${delim}bits${delim}user (),
+    .io_mem_${i}_ar_valid (ar_valid_delay_$i),
+    .io_mem_${i}_ar_ready (ar_ready_delay_$i),
+    .io_mem_${i}_ar_bits_addr (ar_addr_delay_$i),
+    .io_mem_${i}_ar_bits_id (ar_id_delay_$i),
+    .io_mem_${i}_ar_bits_size (ar_size_delay_$i),
+    .io_mem_${i}_ar_bits_len (ar_len_delay_$i),
+    .io_mem_${i}_ar_bits_burst (),
+    .io_mem_${i}_ar_bits_lock (),
+    .io_mem_${i}_ar_bits_cache (),
+    .io_mem_${i}_ar_bits_prot (),
+    .io_mem_${i}_ar_bits_qos (),
+    .io_mem_${i}_ar_bits_region (),
+    .io_mem_${i}_ar_bits_user (),
 
-    .io${delim}mem${delim}${i}${delim}aw${delim}valid (aw_valid_delay_$i),
-    .io${delim}mem${delim}${i}${delim}aw${delim}ready (aw_ready_delay_$i),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}addr (aw_addr_delay_$i),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}id (aw_id_delay_$i),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}size (aw_size_delay_$i),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}len (aw_len_delay_$i),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}burst (),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}lock (),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}cache (),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}prot (),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}qos (),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}region (),
-    .io${delim}mem${delim}${i}${delim}aw${delim}bits${delim}user (),
+    .io_mem_${i}_aw_valid (aw_valid_delay_$i),
+    .io_mem_${i}_aw_ready (aw_ready_delay_$i),
+    .io_mem_${i}_aw_bits_addr (aw_addr_delay_$i),
+    .io_mem_${i}_aw_bits_id (aw_id_delay_$i),
+    .io_mem_${i}_aw_bits_size (aw_size_delay_$i),
+    .io_mem_${i}_aw_bits_len (aw_len_delay_$i),
+    .io_mem_${i}_aw_bits_burst (),
+    .io_mem_${i}_aw_bits_lock (),
+    .io_mem_${i}_aw_bits_cache (),
+    .io_mem_${i}_aw_bits_prot (),
+    .io_mem_${i}_aw_bits_qos (),
+    .io_mem_${i}_aw_bits_region (),
+    .io_mem_${i}_aw_bits_user (),
 
-    .io${delim}mem${delim}${i}${delim}w${delim}valid (w_valid_delay_$i),
-    .io${delim}mem${delim}${i}${delim}w${delim}ready (w_ready_delay_$i),
-    .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}strb (w_strb_delay_$i),
-    .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}data (w_data_delay_$i),
-    .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}last (w_last_delay_$i),
-    .io${delim}mem${delim}${i}${delim}w${delim}bits${delim}user (),
+    .io_mem_${i}_w_valid (w_valid_delay_$i),
+    .io_mem_${i}_w_ready (w_ready_delay_$i),
+    .io_mem_${i}_w_bits_strb (w_strb_delay_$i),
+    .io_mem_${i}_w_bits_data (w_data_delay_$i),
+    .io_mem_${i}_w_bits_last (w_last_delay_$i),
+    .io_mem_${i}_w_bits_user (),
 
-    .io${delim}mem${delim}${i}${delim}r${delim}valid (r_valid_delay_$i),
-    .io${delim}mem${delim}${i}${delim}r${delim}ready (r_ready_delay_$i),
-    .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}resp (r_resp_delay_$i),
-    .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}id (r_id_delay_$i),
-    .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}data (r_data_delay_$i),
-    .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}last (r_last_delay_$i),
-    .io${delim}mem${delim}${i}${delim}r${delim}bits${delim}user (1'b0),
+    .io_mem_${i}_r_valid (r_valid_delay_$i),
+    .io_mem_${i}_r_ready (r_ready_delay_$i),
+    .io_mem_${i}_r_bits_resp (r_resp_delay_$i),
+    .io_mem_${i}_r_bits_id (r_id_delay_$i),
+    .io_mem_${i}_r_bits_data (r_data_delay_$i),
+    .io_mem_${i}_r_bits_last (r_last_delay_$i),
+    .io_mem_${i}_r_bits_user (1'b0),
 
-    .io${delim}mem${delim}${i}${delim}b${delim}valid (b_valid_delay_$i),
-    .io${delim}mem${delim}${i}${delim}b${delim}ready (b_ready_delay_$i),
-    .io${delim}mem${delim}${i}${delim}b${delim}bits${delim}resp (b_resp_delay_$i),
-    .io${delim}mem${delim}${i}${delim}b${delim}bits${delim}id (b_id_delay_$i),
-    .io${delim}mem${delim}${i}${delim}b${delim}bits${delim}user (1'b0),
+    .io_mem_${i}_b_valid (b_valid_delay_$i),
+    .io_mem_${i}_b_ready (b_ready_delay_$i),
+    .io_mem_${i}_b_bits_resp (b_resp_delay_$i),
+    .io_mem_${i}_b_bits_id (b_id_delay_$i),
+    .io_mem_${i}_b_bits_user (1'b0),
 
 """ } mkString
 
@@ -233,35 +229,35 @@ object TestBenchGeneration extends FileSystemUtilities {
     $nasti_connections
 
 `ifndef FPGA
-    .io${delim}host${delim}clk(htif_clk),
-    .io${delim}host${delim}clk_edge(),
-    .io${delim}host${delim}debug_stats_csr(htif_out_stats_delay),
+    .io_host_clk(htif_clk),
+    .io_host_clk_edge(),
+    .io_host_debug_stats_csr(htif_out_stats_delay),
 
 `ifdef MEM_BACKUP_EN
-    .io${delim}mem_backup_ctrl${delim}en(1'b1),
+    .io_mem_backup_ctrl_en(1'b1),
 `else
-    .io${delim}mem_backup_ctrl${delim}en(1'b0),
+    .io_mem_backup_ctrl_en(1'b0),
 `endif // MEM_BACKUP_EN
-    .io${delim}mem_backup_ctrl${delim}in_valid(mem_bk_in_valid_delay),
-    .io${delim}mem_backup_ctrl${delim}out_ready(mem_bk_out_ready_delay),
-    .io${delim}mem_backup_ctrl${delim}out_valid(mem_bk_out_valid_delay),
+    .io_mem_backup_ctrl_in_valid(mem_bk_in_valid_delay),
+    .io_mem_backup_ctrl_out_ready(mem_bk_out_ready_delay),
+    .io_mem_backup_ctrl_out_valid(mem_bk_out_valid_delay),
 `else
-    .io${delim}host${delim}clk (),
-    .io${delim}host${delim}clk_edge (),
-    .io${delim}host${delim}debug_stats_csr (),
+    .io_host_clk (),
+    .io_host_clk_edge (),
+    .io_host_debug_stats_csr (),
 
-    .io${delim}mem_backup_ctrl${delim}en (1'b0),
-    .io${delim}mem_backup_ctrl${delim}in_valid (1'b0),
-    .io${delim}mem_backup_ctrl${delim}out_ready (1'b0),
-    .io${delim}mem_backup_ctrl${delim}out_valid (),
+    .io_mem_backup_ctrl_en (1'b0),
+    .io_mem_backup_ctrl_in_valid (1'b0),
+    .io_mem_backup_ctrl_out_ready (1'b0),
+    .io_mem_backup_ctrl_out_valid (),
 `endif // FPGA
 
-    .io${delim}host${delim}in${delim}valid(htif_in_valid_delay),
-    .io${delim}host${delim}in${delim}ready(htif_in_ready_delay),
-    .io${delim}host${delim}in${delim}bits(htif_in_bits_delay),
-    .io${delim}host${delim}out${delim}valid(htif_out_valid_delay),
-    .io${delim}host${delim}out${delim}ready(htif_out_ready_delay),
-    .io${delim}host${delim}out${delim}bits(htif_out_bits_delay)
+    .io_host_in_valid(htif_in_valid_delay),
+    .io_host_in_ready(htif_in_ready_delay),
+    .io_host_in_bits(htif_in_bits_delay),
+    .io_host_out_valid(htif_out_valid_delay),
+    .io_host_out_ready(htif_out_ready_delay),
+    .io_host_out_bits(htif_out_bits_delay)
   );
 """
 
diff --git a/src/main/scala/Testing.scala b/src/main/scala/Testing.scala
index 7edf21a6..7e157d34 100644
--- a/src/main/scala/Testing.scala
+++ b/src/main/scala/Testing.scala
@@ -187,12 +187,6 @@ object TestGenerator extends App with FileSystemUtilities {
   val projectName = args(0)
   val topModuleName = args(1)
   val configClassName = args(2)
-  val chiselVersion = try {
-    args(3).toInt
-  } catch {
-    case e => throwException("4th argument must be CHISEL_VERSION")
-  }
-  require(chiselVersion == 2 || chiselVersion == 3)
   val config = try {
       Class.forName(s"$projectName.$configClassName").newInstance.asInstanceOf[Config]
     } catch {
@@ -215,8 +209,7 @@ object TestGenerator extends App with FileSystemUtilities {
   TestGeneration.generateMakefrag(topModuleName, configClassName)
   TestBenchGeneration.generateVerilogFragment(
     topModuleName, configClassName,
-    paramsFromConfig(NMemoryChannels),
-    chiselVersion)
+    paramsFromConfig(NMemoryChannels))
   TestBenchGeneration.generateCPPFragment(
     topModuleName, configClassName,
     paramsFromConfig(NMemoryChannels))
diff --git a/vsim/Makefrag b/vsim/Makefrag
index e26fb0e8..a6e9e143 100644
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@@ -46,7 +46,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(sim_dir)/libdramsim.a \
 	+incdir+$(generated_dir) \
 	+define+CLOCK_PERIOD=0.5 $(sim_vsrcs) $(sim_csrcs) \
-	+define+PRINTF_COND="$(TB).verbose && !$(TB).reset" \
+	+define+PRINTF_COND=$(TB).verbose \
 	+libext+.v \
 
 #--------------------------------------------------------------------
diff --git a/vsim/Makefrag-verilog b/vsim/Makefrag-verilog
index 30317b68..66034bc2 100644
--- a/vsim/Makefrag-verilog
+++ b/vsim/Makefrag-verilog
@@ -11,14 +11,14 @@ $(generated_dir)/$(MODEL).$(CONFIG).v $(generated_dir)/$(MODEL).$(CONFIG).d $(ge
 	fi
 
 $(generated_dir)/memdessertMemDessert.$(CONFIG).v $(generated_dir)/memdessertMemDessert.$(CONFIG).d: $(base_dir)/$(src_path)/*.scala $(base_dir)/uncore/$(src_path)/*.scala
-	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) $(CHISEL_VERSION) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
+	cd $(base_dir) && mkdir -p $(generated_dir) && $(SBT) "run $(PROJECT) MemDessert $(CONFIG) --backend v --targetDir $(generated_dir) --W0W --moduleNamePrefix memdessert --configName $(CONFIG)"
 
 else
 
 FIRRTL ?= $(base_dir)/firrtl/utils/bin/firrtl
 
 $(FIRRTL):
-	$(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build-scala
+	$(MAKE) -C $(base_dir)/firrtl root_dir=$(base_dir)/firrtl build
 
 # If I don't mark these as .SECONDARY then make will delete these internal
 # files.
@@ -27,7 +27,7 @@ $(FIRRTL):
 
 $(generated_dir)/%.$(CONFIG).fir: $(chisel_srcs)
 	mkdir -p $(dir $@)
-	cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(notdir $@)) $(CONFIG) $(CHISEL_VERSION) $(CHISEL_ARGS) --configDump --noInlineMem"
+	cd $(base_dir) && $(SBT) "run $(PROJECT) $(patsubst %.$(CONFIG).fir,%,$(notdir $@)) $(CONFIG) $(CHISEL_ARGS) --configDump --noInlineMem"
 	mv $(patsubst %.$(CONFIG).fir,%.fir,$@) $@
 
 $(generated_dir)/%.v $(generated_dir)/%.prm: $(generated_dir)/%.fir $(FIRRTL)