riscv/rocket-chip
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initial commit of rocket chisel project, riscv assembly tests and benchmarks

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Rimas Avizienis
2011-10-25 23:02:47 -07:00
commit c06e2d16e4
18 changed files with 2699 additions and 0 deletions
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rocket/src/main/scala/instructions.scala Normal file
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package Top {
import Chisel._
import Node._;
object Instructions
{
val UNIMP = Bits("b00000000000000000000000000000000", 32);
val J = Bits("b?????????????????????????_1100111", 32);
val JAL = Bits("b?????????????????????????_1101111", 32);
val JALR_C = Bits("b?????_?????_????????????_000_1101011", 32);
val JALR_R = Bits("b?????_?????_????????????_001_1101011", 32);
val JALR_J = Bits("b?????_?????_????????????_010_1101011", 32);
val BEQ = Bits("b?????_?????_?????_???????_000_1100011", 32);
val BNE = Bits("b?????_?????_?????_???????_001_1100011", 32);
val BLT = Bits("b?????_?????_?????_???????_100_1100011", 32);
val BGE = Bits("b?????_?????_?????_???????_101_1100011", 32);
val BLTU = Bits("b?????_?????_?????_???????_110_1100011", 32);
val BGEU = Bits("b?????_?????_?????_???????_111_1100011", 32);
val LUI = Bits("b?????_????????????????????_0110111", 32);
val ADDI = Bits("b?????_?????_????????????_000_0010011", 32);
val SLLI = Bits("b?????_?????_000000_??????_001_0010011", 32);
val SLTI = Bits("b?????_?????_????????????_010_0010011", 32);
val SLTIU = Bits("b?????_?????_????????????_011_0010011", 32);
val XORI = Bits("b?????_?????_????????????_100_0010011", 32);
val SRLI = Bits("b?????_?????_000000_??????_101_0010011", 32);
val SRAI = Bits("b?????_?????_000001_??????_101_0010011", 32);
val ORI = Bits("b?????_?????_????????????_110_0010011", 32);
val ANDI = Bits("b?????_?????_????????????_111_0010011", 32);
val ADD = Bits("b?????_?????_?????_0000000000_0110011", 32);
val SUB = Bits("b?????_?????_?????_1000000000_0110011", 32);
val SLL = Bits("b?????_?????_?????_0000000001_0110011", 32);
val SLT = Bits("b?????_?????_?????_0000000010_0110011", 32);
val SLTU = Bits("b?????_?????_?????_0000000011_0110011", 32);
val riscvXOR = Bits("b?????_?????_?????_0000000100_0110011", 32);
val SRL = Bits("b?????_?????_?????_0000000101_0110011", 32);
val SRA = Bits("b?????_?????_?????_1000000101_0110011", 32);
val riscvOR = Bits("b?????_?????_?????_0000000110_0110011", 32);
val riscvAND = Bits("b?????_?????_?????_0000000111_0110011", 32);
val MUL = Bits("b?????_?????_?????_0000001000_0110011", 32);
val MULH = Bits("b?????_?????_?????_0000001001_0110011", 32);
val MULHSU = Bits("b?????_?????_?????_0000001010_0110011", 32);
val MULHU = Bits("b?????_?????_?????_0000001011_0110011", 32);
val DIV = Bits("b?????_?????_?????_0000001100_0110011", 32);
val DIVU = Bits("b?????_?????_?????_0000001101_0110011", 32);
val REM = Bits("b?????_?????_?????_0000001110_0110011", 32);
val REMU = Bits("b?????_?????_?????_0000001111_0110011", 32);
val ADDIW = Bits("b?????_?????_????????????_000_0011011", 32);
val SLLIW = Bits("b?????_?????_000000_0_?????_001_0011011", 32);
val SRLIW = Bits("b?????_?????_000000_0_?????_101_0011011", 32);
val SRAIW = Bits("b?????_?????_000001_0_?????_101_0011011", 32);
val ADDW = Bits("b?????_?????_?????_0000000000_0111011", 32);
val SUBW = Bits("b?????_?????_?????_1000000000_0111011", 32);
val SLLW = Bits("b?????_?????_?????_0000000001_0111011", 32);
val SRLW = Bits("b?????_?????_?????_0000000101_0111011", 32);
val SRAW = Bits("b?????_?????_?????_1000000101_0111011", 32);
val MULW = Bits("b?????_?????_?????_0000001000_0111011", 32);
val DIVW = Bits("b?????_?????_?????_0000001100_0111011", 32);
val DIVUW = Bits("b?????_?????_?????_0000001101_0111011", 32);
val REMW = Bits("b?????_?????_?????_0000001110_0111011", 32);
val REMUW = Bits("b?????_?????_?????_0000001111_0111011", 32);
val LB = Bits("b?????_?????_????????????_000_0000011", 32);
val LH = Bits("b?????_?????_????????????_001_0000011", 32);
val LW = Bits("b?????_?????_????????????_010_0000011", 32);
val LD = Bits("b?????_?????_????????????_011_0000011", 32);
val LBU = Bits("b?????_?????_????????????_100_0000011", 32);
val LHU = Bits("b?????_?????_????????????_101_0000011", 32);
val LWU = Bits("b?????_?????_????????????_110_0000011", 32);
val SB = Bits("b?????_?????_?????_???????_000_0100011", 32);
val SH = Bits("b?????_?????_?????_???????_001_0100011", 32);
val SW = Bits("b?????_?????_?????_???????_010_0100011", 32);
val SD = Bits("b?????_?????_?????_???????_011_0100011", 32);
val AMOADD_W = Bits("b?????_?????_?????_00000_000_10_1000011", 32);
val AMOSWAP_W = Bits("b?????_?????_?????_00000_010_10_1000011", 32);
val AMOAND_W = Bits("b?????_?????_?????_00000_100_10_1000011", 32);
val AMOOR_W = Bits("b?????_?????_?????_00000_110_10_1000011", 32);
val AMOMIN_W = Bits("b?????_?????_?????_00001_000_10_1000011", 32);
val AMOMAX_W = Bits("b?????_?????_?????_00001_010_10_1000011", 32);
val AMOMINU_W = Bits("b?????_?????_?????_00001_100_10_1000011", 32);
val AMOMAXU_W = Bits("b?????_?????_?????_00001_110_10_1000011", 32);
val AMOADD_D = Bits("b?????_?????_?????_00000_000_11_1000011", 32);
val AMOSWAP_D = Bits("b?????_?????_?????_00000_010_11_1000011", 32);
val AMOAND_D = Bits("b?????_?????_?????_00000_100_11_1000011", 32);
val AMOOR_D = Bits("b?????_?????_?????_00000_110_11_1000011", 32);
val AMOMIN_D = Bits("b?????_?????_?????_00001_000_11_1000011", 32);
val AMOMAX_D = Bits("b?????_?????_?????_00001_010_11_1000011", 32);
val AMOMINU_D = Bits("b?????_?????_?????_00001_100_11_1000011", 32);
val AMOMAXU_D = Bits("b?????_?????_?????_00001_110_11_1000011", 32);
val FENCE = Bits("b?????_?????_????????????_010_0101111", 32);
val FENCE_I = Bits("b?????_?????_????????????_001_0101111", 32);
val RDNPC = Bits("b?????_00000_00000_0000000000_0010111", 32);
val SYNCI = Bits("b00000_00000_00000_0000000001_0010111", 32);
val SYNC = Bits("b00000_00000_00000_0000000010_0010111", 32);
val SYSCALL = Bits("b00000_00000_00000_0000000000_1110111", 32);
val BREAK = Bits("b00000_00000_00000_0000000001_1110111", 32);
val EI = Bits("b?????_00000_00000_0000000000_1111011", 32);
val DI = Bits("b?????_00000_00000_0000000001_1111011", 32);
val MFPCR = Bits("b?????_00000_?????_0000000010_1111011", 32);
val MTPCR = Bits("b00000_?????_?????_0000000011_1111011", 32);
val ERET = Bits("b00000_00000_00000_0000000100_1111011", 32);
val FADD_S = Bits("b?????_?????_?????_00000_???_00_1010011", 32);
val FSUB_S = Bits("b?????_?????_?????_00001_???_00_1010011", 32);
val FMUL_S = Bits("b?????_?????_?????_00010_???_00_1010011", 32);
val FDIV_S = Bits("b?????_?????_?????_00011_???_00_1010011", 32);
val FSQRT_S = Bits("b?????_?????_00000_00100_???_00_1010011", 32);
val FSGNJ_S = Bits("b?????_?????_?????_0010111100_1010011", 32);
val FSGNJN_S = Bits("b?????_?????_?????_0011011100_1010011", 32);
val FSGNJX_S = Bits("b?????_?????_?????_0011111100_1010011", 32);
val FADD_D = Bits("b?????_?????_?????_00000_???_01_1010011", 32);
val FSUB_D = Bits("b?????_?????_?????_00001_???_01_1010011", 32);
val FMUL_D = Bits("b?????_?????_?????_00010_???_01_1010011", 32);
val FDIV_D = Bits("b?????_?????_?????_00011_???_01_1010011", 32);
val FSQRT_D = Bits("b?????_?????_00000_00100_???_01_1010011", 32);
val FSGNJ_D = Bits("b?????_?????_?????_0010111101_1010011", 32);
val FSGNJN_D = Bits("b?????_?????_?????_0011011101_1010011", 32);
val FSGNJX_D = Bits("b?????_?????_?????_0011111101_1010011", 32);
val FCVT_L_S = Bits("b?????_?????_00000_01000_???_00_1010011", 32);
val FCVT_LU_S = Bits("b?????_?????_00000_01001_???_00_1010011", 32);
val FCVT_W_S = Bits("b?????_?????_00000_01010_???_00_1010011", 32);
val FCVT_WU_S = Bits("b?????_?????_00000_01011_???_00_1010011", 32);
val FCVT_L_D = Bits("b?????_?????_00000_01000_???_01_1010011", 32);
val FCVT_LU_D = Bits("b?????_?????_00000_01001_???_01_1010011", 32);
val FCVT_W_D = Bits("b?????_?????_00000_01010_???_01_1010011", 32);
val FCVT_WU_D = Bits("b?????_?????_00000_01011_???_01_1010011", 32);
val FCVT_S_L = Bits("b?????_?????_00000_01100_???_00_1010011", 32);
val FCVT_S_LU = Bits("b?????_?????_00000_01101_???_00_1010011", 32);
val FCVT_S_W = Bits("b?????_?????_00000_01110_???_00_1010011", 32);
val FCVT_S_WU = Bits("b?????_?????_00000_01111_???_00_1010011", 32);
val FCVT_D_L = Bits("b?????_?????_00000_01100_???_01_1010011", 32);
val FCVT_D_LU = Bits("b?????_?????_00000_01101_???_01_1010011", 32);
val FCVT_D_W = Bits("b?????_?????_00000_0111011101_1010011", 32);
val FCVT_D_WU = Bits("b?????_?????_00000_0111111101_1010011", 32);
val FCVT_S_D = Bits("b?????_?????_00000_10001_???_00_1010011", 32);
val FCVT_D_S = Bits("b?????_?????_00000_10000_???_01_1010011", 32);
val FEQ_S = Bits("b?????_?????_?????_1010111100_1010011", 32);
val FLT_S = Bits("b?????_?????_?????_1011011100_1010011", 32);
val FLE_S = Bits("b?????_?????_?????_1011111100_1010011", 32);
val FEQ_D = Bits("b?????_?????_?????_1010111101_1010011", 32);
val FLT_D = Bits("b?????_?????_?????_1011011101_1010011", 32);
val FLE_D = Bits("b?????_?????_?????_1011111101_1010011", 32);
val MFTX_S = Bits("b?????_00000_?????_1100011100_1010011", 32);
val MFTX_D = Bits("b?????_00000_?????_1100011101_1010011", 32);
val MFFSR = Bits("b?????_00000_00000_1101111100_1010011", 32);
val MXTF_S = Bits("b?????_?????_00000_1110011100_1010011", 32);
val MXTF_D = Bits("b?????_?????_00000_1110011101_1010011", 32);
val MTFSR = Bits("b00000_?????_00000_1110111100_1010011", 32);
val FLW = Bits("b?????_?????_????????????_010_0000111", 32);
val FLD = Bits("b?????_?????_????????????_011_0000111", 32);
val FSW = Bits("b?????_?????_?????_???????_010_0100111", 32);
val FSD = Bits("b?????_?????_?????_???????_011_0100111", 32);
val FMADD_S = Bits("b?????_?????_?????_?????_???_00_1000011", 32);
val FMSUB_S = Bits("b?????_?????_?????_?????_???_00_1000111", 32);
val FNMSUB_S = Bits("b?????_?????_?????_?????_???_00_1001011", 32);
val FNMADD_S = Bits("b?????_?????_?????_?????_???_00_1001111", 32);
val FMADD_D = Bits("b?????_?????_?????_?????_???_01_1000011", 32);
val FMSUB_D = Bits("b?????_?????_?????_?????_???_01_1000111", 32);
val FNMSUB_D = Bits("b?????_?????_?????_?????_???_01_1001011", 32);
val FNMADD_D = Bits("b?????_?????_?????_?????_???_01_1001111", 32);
val NOP = ADDI & Bits("b00000000000000000000001111111111", 32);
val CFLUSH = Bits("b00000_00000_00000_0000000101_1111011", 32);
}
}