From c06884b78c000bdb422640c29bf2b84d72e89cfc Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Mon, 11 Jan 2016 16:19:21 -0800
Subject: [PATCH] lowercase SMI to Smi

---
 groundtest                      |  2 +-
 junctions                       |  2 +-
 src/main/scala/RocketChip.scala | 12 ++++++------
 uncore                          |  2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)

diff --git a/groundtest b/groundtest
index 5cacda85..c68ceb65 160000
--- a/groundtest
+++ b/groundtest
@@ -1 +1 @@
-Subproject commit 5cacda85cf3e5cf07d8cdabdd8a90df2a0a29539
+Subproject commit c68ceb653184ad06998cb0702f30e39aaaf50b5c
diff --git a/junctions b/junctions
index ee032b02..b4c81b6e 160000
--- a/junctions
+++ b/junctions
@@ -1 +1 @@
-Subproject commit ee032b025af50e5f87ff5da51ad196c354a6b182
+Subproject commit b4c81b6ea5f3f4297469ccff3bd979695630bf92
diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala
index 0539a2f7..cb39eb88 100644
--- a/src/main/scala/RocketChip.scala
+++ b/src/main/scala/RocketChip.scala
@@ -166,7 +166,7 @@ class Uncore(implicit val p: Parameters) extends Module
     io.htif(i).id := htif.io.cpu(i).id
     htif.io.cpu(i).debug_stats_csr <> io.htif(i).debug_stats_csr
 
-    val csr_arb = Module(new SMIArbiter(2, xLen, csrAddrBits))
+    val csr_arb = Module(new SmiArbiter(2, xLen, csrAddrBits))
     csr_arb.io.in(0) <> htif.io.cpu(i).csr
     csr_arb.io.in(1) <> outmemsys.io.csr(i)
     io.htif(i).csr <> csr_arb.io.out
@@ -174,7 +174,7 @@ class Uncore(implicit val p: Parameters) extends Module
 
   // Arbitrate SCR access between MMIO and HTIF
   val scrFile = Module(new SCRFile)
-  val scrArb = Module(new SMIArbiter(2, scrDataBits, scrAddrBits))
+  val scrArb = Module(new SmiArbiter(2, scrDataBits, scrAddrBits))
   scrArb.io.in(0) <> htif.io.scr
   scrArb.io.in(1) <> outmemsys.io.scr
   scrFile.io.smi <> scrArb.io.out
@@ -209,8 +209,8 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
     val mem = Vec(new NastiIO, nMemChannels)
     val mem_backup = new MemSerializedIO(htifW)
     val mem_backup_en = Bool(INPUT)
-    val csr = Vec(new SMIIO(xLen, csrAddrBits), nTiles)
-    val scr = new SMIIO(xLen, scrAddrBits)
+    val csr = Vec(new SmiIO(xLen, csrAddrBits), nTiles)
+    val scr = new SmiIO(xLen, scrAddrBits)
     val mmio = new NastiIO
     val deviceTree = new NastiIO
     val dma = (new DmaIO).flip
@@ -285,12 +285,12 @@ class OuterMemorySystem(implicit val p: Parameters) extends Module with HasTopLe
   for (i <- 0 until nTiles) {
     val csrName = s"conf:csr$i"
     val csrPort = addrHashMap(csrName).port
-    val conv = Module(new SMIIONastiIOConverter(xLen, csrAddrBits))
+    val conv = Module(new SmiIONastiIOConverter(xLen, csrAddrBits))
     conv.io.nasti <> interconnect.io.slaves(csrPort)
     io.csr(i) <> conv.io.smi
   }
 
-  val src_conv = Module(new SMIIONastiIOConverter(scrDataBits, scrAddrBits))
+  val src_conv = Module(new SmiIONastiIOConverter(scrDataBits, scrAddrBits))
   src_conv.io.nasti <> interconnect.io.slaves(addrHashMap("conf:scr").port)
   io.scr <> src_conv.io.smi
 
diff --git a/uncore b/uncore
index 1e6c22a6..aa5bf542 160000
--- a/uncore
+++ b/uncore
@@ -1 +1 @@
-Subproject commit 1e6c22a60c6eccbb85cecadf7503be8eb4c1e476
+Subproject commit aa5bf542f2bdb39a73a64673ad8a84366ddbfc03