update for rocket-chip release

src/main/scala/Backends.scala

@@ -1,14 +1,14 @@
-package referencechip
+package rocketchip
 
 import Chisel._
-import ReferenceChipBackend._
+import RocketChipBackend._
 import scala.collection.mutable.HashMap
 
-object ReferenceChipBackend {
+object RocketChipBackend {
   val initMap = new HashMap[Module, Bool]()
 }
 
-class ReferenceChipBackend extends VerilogBackend
+class RocketChipBackend extends VerilogBackend
 {
   initMap.clear()
   override def emitPortDef(m: MemAccess, idx: Int) = {
@@ -65,5 +65,5 @@ class ReferenceChipBackend extends VerilogBackend
   transforms += ((c: Module) => collectNodesIntoComp(initializeDFS))
 }
 
-class Fame1ReferenceChipBackend extends ReferenceChipBackend with Fame1Transform
+class Fame1RocketChipBackend extends RocketChipBackend with Fame1Transform
 

src/main/scala/RocketChip.scala

@@ -1,4 +1,4 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 import uncore._
@@ -68,7 +68,7 @@ class OuterMemorySystem(htif_width: Int)(implicit conf: UncoreConfiguration) ext
     (llc, mes)
   }
 
-  val net = Module(new ReferenceChipCrossbarNetwork)
+  val net = Module(new RocketChipCrossbarNetwork)
   net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
   net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
   masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }
@@ -233,7 +233,7 @@ class Top extends Module {
   val hc = hwacha.HwachaConfiguration(as, vic, dc, 8, 256, ndtlb = 8, nptlb = 2)
   val fpu = if (HAS_FPU) Some(FPUConfig(sfmaLatency = 2, dfmaLatency = 3)) else None
   val rc = RocketConfiguration(tl, as, ic, dc, fpu
-  //                             rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
+                               ,rocc = (c: RocketConfiguration) => (new hwacha.Hwacha(hc, c))
                               )
 
   val io = new VLSITopIO(HTIF_WIDTH)

src/main/scala/fpga.scala

@@ -1,10 +1,8 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 import uncore._
 import rocket._
-import DRAMModel._
-import DRAMModel.MemModelConstants._
 
 
 import DesignSpaceConstants._
@@ -26,7 +24,7 @@ class FPGAOuterMemorySystem(htif_width: Int)(implicit conf: FPGAUncoreConfigurat
     refill_cycles=refill_cycles, tagLeaf=llc_tag_leaf, dataLeaf=llc_data_leaf))
   val masterEndpoints = (0 until ln.nMasters).map(i => Module(new L2CoherenceAgent(i)))
 
-  val net = Module(new ReferenceChipCrossbarNetwork)
+  val net = Module(new RocketChipCrossbarNetwork)
   net.io.clients zip (io.tiles :+ io.htif) map { case (net, end) => net <> end }
   net.io.masters zip (masterEndpoints.map(_.io.inner)) map { case (net, end) => net <> end }
   masterEndpoints.map{ _.io.incoherent zip io.incoherent map { case (m, c) => m := c } }

src/main/scala/network.scala

@@ -1,4 +1,4 @@
-package referencechip
+package rocketchip
 
 import Chisel._
 import uncore._
@@ -22,7 +22,7 @@ object TileLinkHeaderOverwriter {
   }
 }
 
-class ReferenceChipCrossbarNetwork(implicit conf: TileLinkConfiguration) 
+class RocketChipCrossbarNetwork(implicit conf: TileLinkConfiguration) 
   extends LogicalNetwork[TileLinkIO]()(conf.ln) {
   implicit val (ln, co) = (conf.ln, conf.co)
   val io = new Bundle {