tilelink2: split suportsAcquire into T and B variants
This commit is contained in:
Wesley W. Terpstra
parent
e03ba637f4
commit
bf7823f1c8
@ -55,7 +55,7 @@ trait CoreplexNetworkModule extends HasCoreplexParameters {
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val prot = (if (manager.supportsGet) "R" else "") +
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(if (manager.supportsPutFull) "W" else "") +
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(if (manager.executable) "X" else "") +
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(if (manager.supportsAcquire) " [C]" else "")
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(if (manager.supportsAcquireB) " [C]" else "")
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manager.address.foreach { a =>
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println(f"\t${manager.name}%s ${a.base}%x - ${a.base+a.mask+1}%x, $prot")
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}
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@ -253,7 +253,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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val access_address = s2_req.addr
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val a_size = s2_req.typ(MT_SZ-2, 0)
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val a_data = Fill(beatWords, pstore1_storegen.data)
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val acquire = if (edge.manager.anySupportAcquire) {
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val acquire = if (edge.manager.anySupportAcquireB) {
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edge.Acquire(a_source, acquire_address, lgCacheBlockBytes, s2_grow_param)._2 // Cacheability checked by tlb
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} else {
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Wire(new TLBundleA(edge.bundle))
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@ -373,7 +373,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) {
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b = probe_bits,
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reportPermissions = TLPermissions.NtoN)
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val voluntaryReleaseMessage = if (edge.manager.anySupportAcquire) {
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val voluntaryReleaseMessage = if (edge.manager.anySupportAcquireB) {
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edge.Release(
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fromSource = UInt(maxUncachedInFlight - 1),
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toAddress = probe_bits.address,
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@ -332,7 +332,7 @@ class MSHRFile(implicit edge: TLEdgeOut, cfg: DCacheConfig, p: Parameters) exten
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}
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// determine if the request is cacheable or not
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val cacheable = edge.manager.supportsAcquireFast(io.req.bits.addr, lgCacheBlockBytes)
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val cacheable = edge.manager.supportsAcquireBFast(io.req.bits.addr, lgCacheBlockBytes)
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val sdq_val = Reg(init=Bits(0, cfg.nSDQ))
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val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))
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@ -73,16 +73,18 @@ class TLB(implicit edge: TLEdgeOut, val p: Parameters) extends Module with HasTL
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val prot_r = fastCheck(_.supportsGet)
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val prot_w = fastCheck(_.supportsPutFull)
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val prot_x = fastCheck(_.executable)
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val cacheable = fastCheck(_.supportsAcquire)
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val cacheable = fastCheck(_.supportsAcquireB)
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val allSizes = TransferSizes(1, cacheBlockBytes)
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val amoSizes = TransferSizes(1, xLen/8)
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edge.manager.managers.foreach { m =>
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require (m.minAlignment >= 4096, s"MemoryMap region ${m.name} must be page-aligned (is ${m.minAlignment})")
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require (!m.supportsGet || m.supportsGet .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsGet} Get, but must support ${allSizes}")
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require (!m.supportsPutFull || m.supportsPutFull .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsPutFull} PutFull, but must support ${allSizes}")
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require (!m.supportsAcquire || m.supportsAcquire.contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquire} Acquire, but must support ${allSizes}")
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require (!m.supportsAcquireB || m.supportsAcquireB .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireB} AcquireB, but must support ${allSizes}")
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require (!m.supportsAcquireT || m.supportsAcquireT .contains(allSizes), s"MemoryMap region ${m.name} only supports ${m.supportsAcquireT} AcquireT, but must support ${allSizes}")
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require (!m.supportsLogical || m.supportsLogical .contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsLogical} Logical, but must support ${amoSizes}")
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require (!m.supportsArithmetic || m.supportsArithmetic.contains(amoSizes), s"MemoryMap region ${m.name} only supports ${m.supportsArithmetic} Arithmetic, but must support ${amoSizes}")
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require (m.supportsAcquireT || !m.supportsPutFull || !m.supportsAcquireB, s"MemoryMap region ${m.name} supports PutFull and AcquireB but not AcquireT")
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}
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val lookup_tag = Cat(io.ptw.ptbr.asid, io.req.bits.vpn(vpnBits-1,0))
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@ -253,7 +253,7 @@ class TLAtomicAutomata(logical: Boolean = true, arithmetic: Boolean = true, conc
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in.d.bits := out.d.bits
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}
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if (edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe) {
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if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
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in.b.valid := out.b.valid
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out.b.ready := in.b.ready
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in.b.bits := out.b.bits
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@ -22,22 +22,24 @@ class TLBroadcast(lineBytes: Int, numTrackers: Int = 4, bufferless: Boolean = fa
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endSinkId = numTrackers,
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managers = mp.managers.map { m =>
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// We are the last level manager
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require (m.regionType != RegionType.CACHED)
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require (m.regionType != RegionType.TRACKED)
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require (!m.supportsAcquire)
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require (!m.supportsAcquireB)
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// We only manage addresses which are uncached
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if (m.regionType == RegionType.UNCACHED && m.supportsGet) {
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if (m.regionType == RegionType.UNCACHED) {
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// The device had better support line transfers
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val lowerBound = max(m.supportsPutFull.min, m.supportsGet.min)
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require (!m.supportsPutFull || m.supportsPutFull.contains(lineBytes))
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require (!m.supportsGet || m.supportsGet .contains(lineBytes))
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m.copy(
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regionType = RegionType.TRACKED,
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supportsAcquire = TransferSizes(lowerBound, lineBytes),
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supportsAcquireB = TransferSizes(lowerBound, lineBytes),
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supportsAcquireT = if (m.supportsPutFull) TransferSizes(lowerBound, lineBytes) else TransferSizes.none,
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// truncate supported accesses to lineBytes (we only ever probe for one line)
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supportsPutFull = TransferSizes(m.supportsPutFull .min, min(m.supportsPutFull .max, lineBytes)),
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supportsPutPartial = TransferSizes(m.supportsPutPartial.min, min(m.supportsPutPartial.max, lineBytes)),
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supportsGet = TransferSizes(m.supportsGet .min, min(m.supportsGet .max, lineBytes)),
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supportsHint = TransferSizes(m.supportsHint .min, min(m.supportsHint .max, lineBytes)),
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supportsArithmetic = TransferSizes(m.supportsArithmetic.min, min(m.supportsArithmetic.max, lineBytes)),
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supportsLogical = TransferSizes(m.supportsLogical .min, min(m.supportsLogical .max, lineBytes)),
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fifoId = None // trackers do not respond in FIFO order!
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)
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} else {
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@ -31,7 +31,7 @@ class TLBuffer(a: Int = 2, b: Int = 2, c: Int = 2, d: Int = 2, e: Int = 2, pipe:
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if (a>0) { out.a <> Queue(in .a, a, pipe && a<2) } else { out.a <> in.a }
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if (d>0) { in .d <> Queue(out.d, d, pipe && d<2) } else { in.d <> out.d }
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if (edgeOut.manager.anySupportAcquire && edgeOut.client.anySupportProbe) {
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if (edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe) {
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if (b>0) { in .b <> Queue(out.b, b, pipe && b<2) } else { in.b <> out.b }
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if (c>0) { out.c <> Queue(in .c, c, pipe && c<2) } else { out.c <> in.c }
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if (e>0) { out.e <> Queue(in .e, e, pipe && e<2) } else { out.e <> in.e }
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@ -20,7 +20,7 @@ class TLAsyncCrossingSource(sync: Int = 3)(implicit p: Parameters) extends LazyM
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val sink_reset_n = out.a.sink_reset_n
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val bce = edgeIn.manager.anySupportAcquire && edgeIn.client.anySupportProbe
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val bce = edgeIn.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
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val depth = edgeOut.manager.depth
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out.a <> ToAsyncBundle(in.a, depth, sync)
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@ -54,7 +54,7 @@ class TLAsyncCrossingSink(depth: Int = 8, sync: Int = 3)(implicit p: Parameters)
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((io.in zip io.out) zip (node.edgesIn zip node.edgesOut)) foreach { case ((in, out), (edgeIn, edgeOut)) =>
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val source_reset_n = in.a.source_reset_n
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val bce = edgeOut.manager.anySupportAcquire && edgeOut.client.anySupportProbe
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val bce = edgeOut.manager.anySupportAcquireB && edgeOut.client.anySupportProbe
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out.a <> FromAsyncBundle(in.a, sync)
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in.d <> ToAsyncBundle(out.d, depth, sync)
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@ -27,7 +27,7 @@ class TLEdge(
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// Do there exist A messages with Data?
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val aDataYes = manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportPutFull || manager.anySupportPutPartial
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// Do there exist A messages without Data?
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val aDataNo = manager.anySupportAcquire || manager.anySupportGet || manager.anySupportHint
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val aDataNo = manager.anySupportAcquireB || manager.anySupportGet || manager.anySupportHint
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// Statically optimize the case where hasData is a constant
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if (!aDataYes) Some(false) else if (!aDataNo) Some(true) else None
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}
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@ -48,9 +48,9 @@ class TLEdge(
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}
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case _:TLBundleD => {
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// Do there eixst D messages with Data?
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val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquire
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val dDataYes = manager.anySupportGet || manager.anySupportArithmetic || manager.anySupportLogical || manager.anySupportAcquireB
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// Do there exist D messages without Data?
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val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquire
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val dDataNo = manager.anySupportPutFull || manager.anySupportPutPartial || manager.anySupportHint || manager.anySupportAcquireT
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if (!dDataYes) Some(false) else if (!dDataNo) Some(true) else None
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}
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case _:TLBundleE => Some(false)
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@ -244,8 +244,8 @@ class TLEdgeOut(
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{
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// Transfers
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def Acquire(fromSource: UInt, toAddress: UInt, lgSize: UInt, growPermissions: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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require (manager.anySupportAcquireB)
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val legal = manager.supportsAcquireBFast(toAddress, lgSize)
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val a = Wire(new TLBundleA(bundle))
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a.opcode := TLMessages.Acquire
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a.param := growPermissions
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@ -258,8 +258,8 @@ class TLEdgeOut(
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}
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def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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require (manager.anySupportAcquireB)
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val legal = manager.supportsAcquireBFast(toAddress, lgSize)
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val c = Wire(new TLBundleC(bundle))
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c.opcode := TLMessages.Release
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c.param := shrinkPermissions
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@ -272,8 +272,8 @@ class TLEdgeOut(
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}
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def Release(fromSource: UInt, toAddress: UInt, lgSize: UInt, shrinkPermissions: UInt, data: UInt) = {
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require (manager.anySupportAcquire)
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val legal = manager.supportsAcquireFast(toAddress, lgSize)
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require (manager.anySupportAcquireB)
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val legal = manager.supportsAcquireBFast(toAddress, lgSize)
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val c = Wire(new TLBundleC(bundle))
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c.opcode := TLMessages.ReleaseData
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c.param := shrinkPermissions
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@ -22,7 +22,8 @@ class TLFilter(select: AddressSet)(implicit p: Parameters) extends LazyModule
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if (filtered.isEmpty) { None } else {
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Some(m.copy(
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address = filtered,
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supportsAcquire = m.supportsAcquire .intersect(cap),
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supportsAcquireT = m.supportsAcquireT .intersect(cap),
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supportsAcquireB = m.supportsAcquireB .intersect(cap),
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supportsArithmetic = m.supportsArithmetic.intersect(cap),
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supportsLogical = m.supportsLogical .intersect(cap),
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supportsGet = m.supportsGet .intersect(cap),
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@ -62,7 +62,7 @@ class TLFragmenter(val minSize: Int, val maxSize: Int, val alwaysMin: Boolean =
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// We don't support fragmenting to sub-beat accesses
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require (minSize >= beatBytes)
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// We can't support devices which are cached on both sides of us
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require (!edgeOut.manager.anySupportAcquire || !edgeIn.client.anySupportProbe)
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require (!edgeOut.manager.anySupportAcquireB || !edgeIn.client.anySupportProbe)
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/* The Fragmenter is a bit tricky, because there are 5 sizes in play:
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* max size -- the maximum transfer size possible
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@ -27,7 +27,7 @@ class TLHintHandler(supportManagers: Boolean = true, supportClients: Boolean = f
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val edgeOut = node.edgesOut(0)
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// Don't add support for clients if there is no BCE channel
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val bce = edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe
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val bce = edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe
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require (!supportClients || bce)
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// Does it even make sense to add the HintHandler?
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@ -57,7 +57,7 @@ class TLIsolation(fOut: (Bool, UInt) => UInt, fIn: (Bool, UInt) => UInt)(implici
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ABo(out.a, in .a)
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ABi(in .d, out.d)
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if (edgeOut.manager.base.anySupportAcquire && edgeOut.client.base.anySupportProbe) {
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if (edgeOut.manager.base.anySupportAcquireB && edgeOut.client.base.anySupportProbe) {
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ABi(in .b, out.b)
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ABo(out.c, in .c)
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ABo(out.e, in .e)
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@ -42,7 +42,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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val mask = edge.full_mask(bundle)
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when (bundle.opcode === TLMessages.Acquire) {
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'A' channel carries Acquire type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'A' channel carries Acquire type unsupported by manager" + extra)
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assert (source_ok, "'A' channel Acquire carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'A' channel Acquire smaller than a beat" + extra)
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assert (is_aligned, "'A' channel Acquire address not aligned to size" + extra)
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@ -189,7 +189,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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}
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when (bundle.opcode === TLMessages.Release) {
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries Release type unsupported by manager" + extra)
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assert (source_ok, "'C' channel Release carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel Release smaller than a beat" + extra)
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assert (is_aligned, "'C' channel Release address not aligned to size" + extra)
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@ -198,7 +198,7 @@ class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
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}
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when (bundle.opcode === TLMessages.ReleaseData) {
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assert (edge.manager.supportsAcquireSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
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assert (edge.manager.supportsAcquireBSafe(edge.address(bundle), bundle.size), "'C' channel carries ReleaseData type unsupported by manager" + extra)
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assert (source_ok, "'C' channel ReleaseData carries invalid source ID" + extra)
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assert (bundle.size >= UInt(log2Ceil(edge.manager.beatBytes)), "'C' channel ReleaseData smaller than a beat" + extra)
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assert (is_aligned, "'C' channel ReleaseData address not aligned to size" + extra)
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@ -12,7 +12,8 @@ case class TLManagerParameters(
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executable: Boolean = false, // processor can execute from this memory
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nodePath: Seq[BaseNode] = Seq(),
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// Supports both Acquire+Release+Finish of these sizes
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supportsAcquire: TransferSizes = TransferSizes.none,
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supportsAcquireT: TransferSizes = TransferSizes.none,
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supportsAcquireB: TransferSizes = TransferSizes.none,
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supportsArithmetic: TransferSizes = TransferSizes.none,
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supportsLogical: TransferSizes = TransferSizes.none,
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supportsGet: TransferSizes = TransferSizes.none,
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@ -28,10 +29,20 @@ case class TLManagerParameters(
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address.combinations(2).foreach { case Seq(x,y) => require (!x.overlaps(y)) }
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require (supportsPutFull.contains(supportsPutPartial))
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require (supportsPutFull.contains(supportsArithmetic))
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require (supportsPutFull.contains(supportsLogical))
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require (supportsGet.contains(supportsArithmetic))
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require (supportsGet.contains(supportsLogical))
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require (supportsAcquireB.contains(supportsAcquireT))
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// Make sure that the regionType agrees with the capabilities
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require ((regionType == RegionType.CACHED || regionType == RegionType.TRACKED) != supportsAcquireB.none)
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require (regionType != RegionType.UNCACHED || supportsGet)
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// Largest support transfer of all types
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val maxTransfer = List(
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supportsAcquire.max,
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supportsAcquireT.max,
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supportsAcquireB.max,
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supportsArithmetic.max,
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supportsLogical.max,
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supportsGet.max,
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@ -73,7 +84,8 @@ case class TLManagerPortParameters(
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def maxTransfer = managers.map(_.maxTransfer).max
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// Operation sizes supported by all outward Managers
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val allSupportAcquire = managers.map(_.supportsAcquire) .reduce(_ intersect _)
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val allSupportAcquireT = managers.map(_.supportsAcquireT) .reduce(_ intersect _)
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val allSupportAcquireB = managers.map(_.supportsAcquireB) .reduce(_ intersect _)
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val allSupportArithmetic = managers.map(_.supportsArithmetic).reduce(_ intersect _)
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val allSupportLogical = managers.map(_.supportsLogical) .reduce(_ intersect _)
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val allSupportGet = managers.map(_.supportsGet) .reduce(_ intersect _)
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@ -82,7 +94,8 @@ case class TLManagerPortParameters(
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val allSupportHint = managers.map(_.supportsHint) .reduce(_ intersect _)
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// Operation supported by at least one outward Managers
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val anySupportAcquire = managers.map(!_.supportsAcquire.none) .reduce(_ || _)
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val anySupportAcquireT = managers.map(!_.supportsAcquireT.none) .reduce(_ || _)
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val anySupportAcquireB = managers.map(!_.supportsAcquireB.none) .reduce(_ || _)
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val anySupportArithmetic = managers.map(!_.supportsArithmetic.none).reduce(_ || _)
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val anySupportLogical = managers.map(!_.supportsLogical.none) .reduce(_ || _)
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val anySupportGet = managers.map(!_.supportsGet.none) .reduce(_ || _)
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@ -122,7 +135,8 @@ case class TLManagerPortParameters(
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}
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// Check for support of a given operation at a specific address
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val supportsAcquireSafe = safe_helper(_.supportsAcquire) _
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val supportsAcquireTSafe = safe_helper(_.supportsAcquireT) _
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val supportsAcquireBSafe = safe_helper(_.supportsAcquireB) _
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val supportsArithmeticSafe = safe_helper(_.supportsArithmetic) _
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val supportsLogicalSafe = safe_helper(_.supportsLogical) _
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val supportsGetSafe = safe_helper(_.supportsGet) _
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@ -130,7 +144,8 @@ case class TLManagerPortParameters(
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val supportsPutPartialSafe = safe_helper(_.supportsPutPartial) _
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val supportsHintSafe = safe_helper(_.supportsHint) _
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||||
val supportsAcquireFast = fast_helper(_.supportsAcquire) _
|
||||
val supportsAcquireTFast = fast_helper(_.supportsAcquireT) _
|
||||
val supportsAcquireBFast = fast_helper(_.supportsAcquireB) _
|
||||
val supportsArithmeticFast = fast_helper(_.supportsArithmetic) _
|
||||
val supportsLogicalFast = fast_helper(_.supportsLogical) _
|
||||
val supportsGetFast = fast_helper(_.supportsGet) _
|
||||
@ -296,7 +311,8 @@ object ManagerUnification
|
||||
regionType: RegionType.T,
|
||||
executable: Boolean,
|
||||
lastNode: BaseNode,
|
||||
supportsAcquire: TransferSizes,
|
||||
supportsAcquireT: TransferSizes,
|
||||
supportsAcquireB: TransferSizes,
|
||||
supportsArithmetic: TransferSizes,
|
||||
supportsLogical: TransferSizes,
|
||||
supportsGet: TransferSizes,
|
||||
@ -307,7 +323,8 @@ object ManagerUnification
|
||||
regionType = x.regionType,
|
||||
executable = x.executable,
|
||||
lastNode = x.nodePath.last,
|
||||
supportsAcquire = x.supportsAcquire,
|
||||
supportsAcquireT = x.supportsAcquireT,
|
||||
supportsAcquireB = x.supportsAcquireB,
|
||||
supportsArithmetic = x.supportsArithmetic,
|
||||
supportsLogical = x.supportsLogical,
|
||||
supportsGet = x.supportsGet,
|
||||
|
||||
@ -31,7 +31,7 @@ class TLSourceShrinker(maxInFlight: Int)(implicit p: Parameters) extends LazyMod
|
||||
|
||||
// Acquires cannot pass this adapter; it makes Probes impossible
|
||||
require (!edgeIn.client.anySupportProbe ||
|
||||
!edgeOut.manager.anySupportAcquire)
|
||||
!edgeOut.manager.anySupportAcquireB)
|
||||
|
||||
out.b.ready := Bool(true)
|
||||
out.c.valid := Bool(false)
|
||||
|
||||
@ -84,9 +84,9 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameter
|
||||
val a_last = edgeIn.last(in.a)
|
||||
|
||||
// Make sure the fields are within the bounds we assumed
|
||||
assert (a_source < UInt(1 << sourceBits))
|
||||
assert (a_size < UInt(1 << sizeBits))
|
||||
assert (a_addr_lo < UInt(1 << addrBits))
|
||||
assert (a_source < UInt(BigInt(1) << sourceBits))
|
||||
assert (a_size < UInt(BigInt(1) << sizeBits))
|
||||
assert (a_addr_lo < UInt(BigInt(1) << addrBits))
|
||||
|
||||
// Carefully pack/unpack fields into the state we send
|
||||
val baseEnd = 0
|
||||
|
||||
@ -147,7 +147,7 @@ class TLWidthWidget(innerBeatBytes: Int)(implicit p: Parameters) extends LazyMod
|
||||
splice(edgeIn, in.a, edgeOut, out.a)
|
||||
splice(edgeOut, out.d, edgeIn, in.d)
|
||||
|
||||
if (edgeOut.manager.anySupportAcquire && edgeIn.client.anySupportProbe) {
|
||||
if (edgeOut.manager.anySupportAcquireB && edgeIn.client.anySupportProbe) {
|
||||
splice(edgeOut, out.b, edgeIn, in.b)
|
||||
splice(edgeIn, in.c, edgeOut, out.c)
|
||||
in.e.ready := out.e.ready
|
||||
|
||||
@ -164,7 +164,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
|
||||
for (o <- 0 until out.size) {
|
||||
val allowI = Seq.tabulate(in.size) { i =>
|
||||
node.edgesIn(i).client.anySupportProbe &&
|
||||
node.edgesOut(o).manager.anySupportAcquire
|
||||
node.edgesOut(o).manager.anySupportAcquireB
|
||||
}
|
||||
TLArbiter(policy)(out(o).a, (beatsAI zip portsAOI(o) ):_*)
|
||||
TLArbiter(policy)(out(o).c, filter(beatsCI zip portsCOI(o), allowI):_*)
|
||||
@ -174,7 +174,7 @@ class TLXbar(policy: TLArbiter.Policy = TLArbiter.lowestIndexFirst)(implicit p:
|
||||
for (i <- 0 until in.size) {
|
||||
val allowO = Seq.tabulate(out.size) { o =>
|
||||
node.edgesIn(i).client.anySupportProbe &&
|
||||
node.edgesOut(o).manager.anySupportAcquire
|
||||
node.edgesOut(o).manager.anySupportAcquireB
|
||||
}
|
||||
TLArbiter(policy)(in(i).b, filter(beatsBO zip portsBIO(i), allowO):_*)
|
||||
TLArbiter(policy)(in(i).d, (beatsDO zip portsDIO(i) ):_*)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user