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tilelink2: split suportsAcquire into T and B variants

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This commit is contained in:
Wesley W. Terpstra
2017-01-17 18:52:16 -08:00
parent e03ba637f4
commit bf7823f1c8
19 changed files with 71 additions and 49 deletions
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6
src/main/scala/uncore/tilelink2/ToAXI4.scala
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@ -84,9 +84,9 @@ class TLToAXI4(idBits: Int, combinational: Boolean = true)(implicit p: Parameter
val a_last = edgeIn.last(in.a)
// Make sure the fields are within the bounds we assumed
assert (a_source < UInt(1 << sourceBits))
assert (a_size < UInt(1 << sizeBits))
assert (a_addr_lo < UInt(1 << addrBits))
assert (a_source < UInt(BigInt(1) << sourceBits))
assert (a_size < UInt(BigInt(1) << sizeBits))
assert (a_addr_lo < UInt(BigInt(1) << addrBits))
// Carefully pack/unpack fields into the state we send
val baseEnd = 0