riscv/rocket-chip
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tilelink2: split suportsAcquire into T and B variants

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Wesley W. Terpstra committed 2017-01-19 19:07:13 -08:00
1 parent e03ba637f4
commit bf7823f1c8
19 files changed
+71 -49
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src/main/scala/rocket/NBDcache.scala
+1 -1
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@@ -332,7 +332,7 @@ class MSHRFile(implicit edge: TLEdgeOut, cfg: DCacheConfig, p: Parameters) exten
}
// determine if the request is cacheable or not
val cacheable = edge.manager.supportsAcquireFast(io.req.bits.addr, lgCacheBlockBytes)
val cacheable = edge.manager.supportsAcquireBFast(io.req.bits.addr, lgCacheBlockBytes)
val sdq_val = Reg(init=Bits(0, cfg.nSDQ))
val sdq_alloc_id = PriorityEncoder(~sdq_val(cfg.nSDQ-1,0))