riscv/rocket-chip
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allow MODEL to be something other than TestHarness

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This commit is contained in:
Howard Mao 2016-09-14 20:04:33 -07:00
parent 8550582f84
commit bf253aaa97
4 changed files with 4 additions and 3 deletions
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2
csrc/emulator.cc
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@ -65,7 +65,7 @@ int main(int argc, char** argv)
srand48(random_seed); srand48(random_seed);
Verilated::randReset(2); Verilated::randReset(2);
VTestHarness *tile = new VTestHarness; MODEL *tile = new MODEL;
#if VM_TRACE #if VM_TRACE
Verilated::traceEverOn(true); // Verilator must compute traced signals Verilated::traceEverOn(true); // Verilator must compute traced signals

2
emulator/Makefrag-verilator
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@ -54,7 +54,7 @@ VERILATOR_FLAGS := --top-module $(MODEL) \
+define+STOP_COND=\$$c\(\"done_reset\"\) --assert \ +define+STOP_COND=\$$c\(\"done_reset\"\) --assert \
-Wno-STMTDLY --x-assign unique \ -Wno-STMTDLY --x-assign unique \
-I$(base_dir)/vsrc \ -I$(base_dir)/vsrc \
-O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h" -O3 -CFLAGS "$(CXXFLAGS) -DVERILATOR -include $(base_dir)/csrc/verilator.h -DMODEL=V$(MODEL)"
cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS))) cppfiles = $(addprefix $(base_dir)/csrc/, $(addsuffix .cc, $(CXXSRCS)))
headers = $(wildcard $(base_dir)/csrc/*.h) headers = $(wildcard $(base_dir)/csrc/*.h)

1
vsim/Makefrag
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@ -51,6 +51,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
$(RISCV)/lib/libfesvr.so \ $(RISCV)/lib/libfesvr.so \
-sverilog \ -sverilog \
+incdir+$(generated_dir) \ +incdir+$(generated_dir) \
+define+MODEL=$(MODEL) \
+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \ +define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
+define+PRINTF_COND=$(TB).printf_cond \ +define+PRINTF_COND=$(TB).printf_cond \
+define+STOP_COND=!$(TB).reset \ +define+STOP_COND=!$(TB).reset \

2
vsrc/TestDriver.v
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@ -87,7 +87,7 @@ module TestDriver;
end end
end end
TestHarness testHarness( `MODEL testHarness(
.clk(clk), .clk(clk),
.reset(reset), .reset(reset),
.io_success(success) .io_success(success)