allow MODEL to be something other than TestHarness

2016-09-14 20:04:33 -07:00
parent 8550582f84
commit bf253aaa97
4 changed files with 4 additions and 3 deletions
--- a/vsim/Makefrag
+++ b/vsim/Makefrag
@ -51,6 +51,7 @@ VCS_OPTS = -notice -line +lint=all,noVCDE,noONGS,noUI -error=PCWM-L -timescale=1
 	$(RISCV)/lib/libfesvr.so \
 	-sverilog \
 	+incdir+$(generated_dir) \
+	+define+MODEL=$(MODEL) \
 	+define+CLOCK_PERIOD=1.0 $(sim_vsrcs) $(sim_csrcs) \
 	+define+PRINTF_COND=$(TB).printf_cond \
 	+define+STOP_COND=!$(TB).reset \