From be8121eeafa28e524f86d5a08637233af28bfb6e Mon Sep 17 00:00:00 2001 From: "Wesley W. Terpstra" Date: Fri, 18 Nov 2016 17:15:57 -0800 Subject: [PATCH] coreplex: fix clock crossing --- src/main/scala/coreplex/Coreplex.scala | 89 ++---------------------- src/main/scala/coreplex/RocketPlex.scala | 66 ++++++++++++++++++ 2 files changed, 72 insertions(+), 83 deletions(-) diff --git a/src/main/scala/coreplex/Coreplex.scala b/src/main/scala/coreplex/Coreplex.scala index ec258dc1..fd6fde18 100644 --- a/src/main/scala/coreplex/Coreplex.scala +++ b/src/main/scala/coreplex/Coreplex.scala @@ -27,94 +27,17 @@ class DefaultCoreplexModule[+L <: DefaultCoreplex, +B <: DefaultCoreplexBundle[L with RocketPlexModule ///// -/* - -trait AsyncConnection { - this: CoreplexNetwork with CoreplexRISCVPlatform => - - val masterCrossings = lazyTiles.map { t => - t.masterNodes map { m => - val crossing = LazyModule(new TLAsyncCrossing) - crossing.node := m - val monitor = (cbus.node := crossing.node) - (crossing, monitor) - } - } - - val slaveCrossings = lazyTiles.map { t => - t.slaveNode map { s => - val crossing = LazyModule(new TLAsyncCrossing) - crossing.node := cbus.node - val monitor = (s := crossing.node) - (crossing, monitor) - } - } -} - -trait AsyncConnectionBundle { - this: CoreplexNetworkBundle with CoreplexRISCVPlatformBundle => - val tcrs = Vec(nTiles, new Bundle { - val clock = Clock(INPUT) - val reset = Bool(INPUT) - }) -} - -trait AsyncConnectionModule { - this: Module with CoreplexNetworkModule with CoreplexRISCVPlatformModule { - val outer: AsyncConnection with CoreplexNetwork with CoreplexRISCVPlatform - val io: AsyncConnectionBundle with CoreplexNetworkBundle with CoreplexRISCVPlatformBundle - } => - - (outer.masterCrossings zip io.tcrs) foreach { case (masters, tcr) => - masters.foreach { case (crossing, monitor) => - crossing.module.io.out_clock := clock - crossing.module.io.out_reset := reset - crossing.module.io.in_clock := tcr.clock - crossing.module.io.in_reset := tcr.reset - monitor.foreach { m => - m.module.clock := clock - m.module.reset := reset - } - } - } - - (outer.slaveCrossings zip io.tcrs) foreach { case (slaves, tcr) => - slaves.foreach { case (crossing, monitor) => - crossing.module.io.in_clock := clock - crossing.module.io.in_reset := reset - crossing.module.io.out_clock := tcr.clock - crossing.module.io.out_reset := tcr.reset - monitor.foreach { m => - m.module.clock := tcr.clock - m.module.reset := tcr.reset - } - } - } - - (tiles.zipWithIndex, io.tcrs).zipped.foreach { case ((tile, i), tcr) => - tile.clock := tcr.clock - tile.reset := tcr.reset - - val ti = tile.io.interrupts - ti.debug := LevelSyncTo(tcr.clock, outer.debug.module.io.debugInterrupts(i)) - ti.mtip := LevelSyncTo(tcr.clock, outer.clint.module.io.tiles(i).mtip) - ti.msip := LevelSyncTo(tcr.clock, outer.clint.module.io.tiles(i).msip) - ti.meip := LevelSyncTo(tcr.clock, outer.tileIntNodes(i).bundleOut(0)(0)) - ti.seip.foreach { _ := LevelSyncTo(tcr.clock, outer.tileIntNodes(i).bundleOut(0)(1)) } - - tile.io.hartid := UInt(i) - tile.io.resetVector := io.resetVector - } -} class MultiClockCoreplex(implicit p: Parameters) extends BaseCoreplex - with AsyncConnection { + with CoreplexRISCVPlatform + with AsyncRocketPlex { override lazy val module = new MultiClockCoreplexModule(this, () => new MultiClockCoreplexBundle(this)) } class MultiClockCoreplexBundle[+L <: MultiClockCoreplex](_outer: L) extends BaseCoreplexBundle(_outer) - with AsyncConnectionBundle + with CoreplexRISCVPlatformBundle + with AsyncRocketPlexBundle class MultiClockCoreplexModule[+L <: MultiClockCoreplex, +B <: MultiClockCoreplexBundle[L]](_outer: L, _io: () => B) extends BaseCoreplexModule(_outer, _io) - with AsyncConnectionModule -*/ + with CoreplexRISCVPlatformModule + with AsyncRocketPlexModule diff --git a/src/main/scala/coreplex/RocketPlex.scala b/src/main/scala/coreplex/RocketPlex.scala index 6b9cc4d4..5c85112e 100644 --- a/src/main/scala/coreplex/RocketPlex.scala +++ b/src/main/scala/coreplex/RocketPlex.scala @@ -39,3 +39,69 @@ trait RocketPlexModule extends CoreplexRISCVPlatformModule { tile.io.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1)) } } + +class AsyncRocketTile(tileId: Int)(implicit p: Parameters) extends LazyModule { + val rocket = LazyModule(new RocketTile(tileId)) + + val cachedOut = TLAsyncOutputNode() + val uncachedOut = TLAsyncOutputNode() + val slaveNode = rocket.slaveNode.map(_ => TLAsyncInputNode()) + + cachedOut := TLAsyncCrossingSource()(rocket.cachedOut) + uncachedOut := TLAsyncCrossingSource()(rocket.uncachedOut) + (rocket.slaveNode zip slaveNode) foreach { case (r,n) => r := TLAsyncCrossingSink()(n) } + + lazy val module = new LazyModuleImp(this) { + val io = new Bundle { + val cached = cachedOut.bundleOut + val uncached = uncachedOut.bundleOut + val slave = slaveNode.map(_.bundleIn) + val hartid = UInt(INPUT, p(XLen)) + val interrupts = new TileInterrupts().asInput + val resetVector = UInt(INPUT, p(XLen)) + } + rocket.module.io.interrupts := ShiftRegister(io.interrupts, 3) + // signals that do not change: + rocket.module.io.hartid := io.hartid + rocket.module.io.resetVector := io.resetVector + } +} + +trait AsyncRocketPlex extends CoreplexRISCVPlatform { + val module: AsyncRocketPlexModule + + val rocketTiles = List.tabulate(p(NTiles)) { i => LazyModule(new AsyncRocketTile(i)) } + val tileIntNodes = rocketTiles.map { _ => IntInternalOutputNode() } + + tileIntNodes.foreach { _ := plic.intnode } + rocketTiles.foreach { r => + r.slaveNode.foreach { _ := TLAsyncCrossingSource()(cbus.node) } + l1tol2.node := TLAsyncCrossingSink()(r.cachedOut) + l1tol2.node := TLAsyncCrossingSink()(r.uncachedOut) + } +} + +trait AsyncRocketPlexBundle extends CoreplexRISCVPlatformBundle { + val outer: CoreplexRISCVPlatform + + val tcrs = Vec(nTiles, new Bundle { + val clock = Clock(INPUT) + val reset = Bool(INPUT) + }) +} + +trait AsyncRocketPlexModule extends CoreplexRISCVPlatformModule { + val outer: AsyncRocketPlex + val io: AsyncRocketPlexBundle + + outer.rocketTiles.map(_.module).zipWithIndex.foreach { case (tile, i) => + tile.clock := io.tcrs(i).clock + tile.reset := io.tcrs(i).reset + tile.io.hartid := UInt(i) + tile.io.resetVector := io.resetVector + tile.io.interrupts := outer.clint.module.io.tiles(i) + tile.io.interrupts.debug := outer.debug.module.io.debugInterrupts(i) + tile.io.interrupts.meip := outer.tileIntNodes(i).bundleOut(0)(0) + tile.io.interrupts.seip.foreach(_ := outer.tileIntNodes(i).bundleOut(0)(1)) + } +}