Generate local interrupt #128 on bus errors

It doesn't have a correpsonding bit in mip/mie, so it isn't individually
maskable, nor is it delegable.

src/main/scala/tile/Core.scala

@@ -81,10 +81,14 @@ abstract class CoreModule(implicit val p: Parameters) extends Module
 abstract class CoreBundle(implicit val p: Parameters) extends ParameterizedBundle()(p)
   with HasCoreParameters
 
+class CoreInterrupts(implicit p: Parameters) extends TileInterrupts()(p) {
+  val buserror = coreParams.tileControlAddr.map(a => Bool())
+}
+
 trait HasCoreIO extends HasTileParameters {
   implicit val p: Parameters
   val io = new CoreBundle()(p) with HasExternallyDrivenTileConstants {
-    val interrupts = new TileInterrupts().asInput
+    val interrupts = new CoreInterrupts().asInput
     val imem  = new FrontendIO
     val dmem = new HellaCacheIO
     val ptw = new DatapathPTWIO().flip

src/main/scala/tile/RocketTile.scala

@@ -150,6 +150,7 @@ class RocketTileModule(outer: RocketTile) extends BaseTileModule(outer, () => ne
   val uncorrectable = RegInit(Bool(false))
 
   decodeCoreInterrupts(core.io.interrupts) // Decode the interrupt vector
+  outer.busErrorUnit.foreach { beu => core.io.interrupts.buserror.get := beu.module.io.interrupt }
   core.io.hartid := io.hartid // Pass through the hartid
   io.trace.foreach { _ := core.io.trace }
   io.halt_and_catch_fire.foreach { _ := uncorrectable }