From 7bef935d2a7aed8329fd37c21ff7043da87902fd Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 3 Nov 2017 15:03:27 -0700 Subject: [PATCH 1/3] Don't emit PTW covers when !usingVM --- src/main/scala/rocket/PTW.scala | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/main/scala/rocket/PTW.scala b/src/main/scala/rocket/PTW.scala index 43fe7497..47192482 100644 --- a/src/main/scala/rocket/PTW.scala +++ b/src/main/scala/rocket/PTW.scala @@ -279,13 +279,11 @@ class PTW(n: Int)(implicit edge: TLEdgeOut, p: Parameters) extends CoreModule()( count := pgLevels-1 } - if (usingVM) { - ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") - ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") - } + ccover(io.mem.s2_nack, "NACK", "D$ nacked page-table access") + ccover(state === s_wait2 && io.mem.s2_xcpt.ae.ld, "AE", "access exception while walking page table") def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = - cover(cond, s"PTW_$label", "MemorySystem;;" + desc) + if (usingVM) cover(cond, s"PTW_$label", "MemorySystem;;" + desc) } /** Mix-ins for constructing tiles that might have a PTW */ From d6ede818eea81ce5641836052edaed437634b9b2 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 3 Nov 2017 15:37:48 -0700 Subject: [PATCH 2/3] DTIM doesn't accept grants --- src/main/scala/rocket/DCache.scala | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index ab43abd3..a00d1606 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -434,7 +434,15 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { // grant val (d_first, d_last, d_done, d_address_inc) = edge.addr_inc(tl_out.d) - val grantIsCached = tl_out.d.bits.opcode.isOneOf(Grant, GrantData) + val grantIsCached = { + val res = tl_out.d.bits.opcode.isOneOf(Grant, GrantData) + if (usingDataScratchpad) { + assert(!(tl_out.d.valid && res)) + false.B + } else { + res + } + } val grantIsUncached = tl_out.d.bits.opcode.isOneOf(AccessAck, AccessAckData, HintAck) val grantIsUncachedData = tl_out.d.bits.opcode === AccessAckData val grantIsVoluntary = tl_out.d.bits.opcode === ReleaseAck // Clears a different pending bit From f859da85ffccd191946d1d03e0c114e3b90b517e Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Fri, 3 Nov 2017 15:38:13 -0700 Subject: [PATCH 3/3] Disable covers that don't apply to DTIM --- src/main/scala/rocket/DCache.scala | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/main/scala/rocket/DCache.scala b/src/main/scala/rocket/DCache.scala index a00d1606..2f14660c 100644 --- a/src/main/scala/rocket/DCache.scala +++ b/src/main/scala/rocket/DCache.scala @@ -645,7 +645,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { val s1_xcpt_valid = tlb.io.req.valid && !s1_nack val s1_xcpt = tlb.io.resp io.cpu.s2_xcpt := Mux(RegNext(s1_xcpt_valid), RegEnable(s1_xcpt, s1_valid_not_nacked), 0.U.asTypeOf(s1_xcpt)) - ccover(s2_valid_pre_xcpt && s2_tl_error, "D_ERROR_REPORTED", "D$ reported TL error to processor") + ccoverNotScratchpad(s2_valid_pre_xcpt && s2_tl_error, "D_ERROR_REPORTED", "D$ reported TL error to processor") when (s2_valid_pre_xcpt && s2_tl_error) { assert(!s2_valid_hit && !s2_uncached) when (s2_write) { io.cpu.s2_xcpt.ae.st := true } @@ -775,7 +775,7 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { io.errors.bus.valid := tl_out.d.fire() && tl_out.d.bits.error io.errors.bus.bits := Mux(grantIsCached, s2_req.addr >> idxLSB << idxLSB, 0.U) - ccover(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") + ccoverNotScratchpad(io.errors.bus.valid && grantIsCached, "D_ERROR_CACHED", "D$ D-channel error, cached") ccover(io.errors.bus.valid && !grantIsCached, "D_ERROR_UNCACHED", "D$ D-channel error, uncached") } @@ -791,4 +791,6 @@ class DCacheModule(outer: DCache) extends HellaCacheModule(outer) { def ccover(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = cover(cond, s"DCACHE_$label", "MemorySystem;;" + desc) + def ccoverNotScratchpad(cond: Bool, label: String, desc: String)(implicit sourceInfo: SourceInfo) = + if (!usingDataScratchpad) ccover(cond, label, desc) }