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Merge pull request #973 from freechipsproject/named_buffers

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systemBus: allowing naming the TLBuffers which get inserted
This commit is contained in:
Megan Wachs 2017-08-24 16:31:14 -07:00 committed by GitHub
commit bdaae40035
1 changed files with 5 additions and 2 deletions
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7
src/main/scala/coreplex/SystemBus.scala
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@ -60,13 +60,16 @@ class SystemBus(params: SystemBusParams)(implicit p: Parameters) extends TLBusWr
sink.node sink.node
} }
def fromSyncPorts(params: BufferParams = BufferParams.default): TLInwardNode = { def fromSyncPorts(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
val buffer = LazyModule(new TLBuffer(params)) val buffer = LazyModule(new TLBuffer(params))
name.foreach{ n => buffer.suggestName(s"${n}_TLBuffer") }
port_fixer.node :=* buffer.node port_fixer.node :=* buffer.node
buffer.node buffer.node
} }
def fromSyncFIFOMaster(params: BufferParams = BufferParams.default): TLInwardNode = fromSyncPorts(params) def fromSyncFIFOMaster(params: BufferParams = BufferParams.default, name: Option[String] = None): TLInwardNode = {
fromSyncPorts(params, name)
}
def fromAsyncPorts(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = { def fromAsyncPorts(depth: Int = 8, sync: Int = 3): TLAsyncInwardNode = {
val sink = LazyModule(new TLAsyncCrossingSink(depth, sync)) val sink = LazyModule(new TLAsyncCrossingSink(depth, sync))