riscv/rocket-chip
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make HTIFModuleIO an anonymous bundle

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This commit is contained in:
Howard Mao 2015-09-10 17:53:42 -07:00
parent 9d89d2a558
commit bd536d8832
1 changed files with 3 additions and 5 deletions
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8
uncore/src/main/scala/htif.scala
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@ -43,15 +43,13 @@ class HTIFIO extends HTIFBundle {
// expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work // expected to be used to quickly indicate to testbench to do logging b/c in 'interesting' work
} }
class HTIFModuleIO extends HTIFBundle { class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val io = new Bundle {
val host = new HostIO val host = new HostIO
val cpu = Vec(new HTIFIO, nCores).flip val cpu = Vec(new HTIFIO, nCores).flip
val mem = new ClientUncachedTileLinkIO val mem = new ClientUncachedTileLinkIO
val scr = new SMIIO(64, scrAddrBits) val scr = new SMIIO(64, scrAddrBits)
} }
class HTIF(pcr_RESET: Int) extends Module with HTIFParameters {
val io = new HTIFModuleIO
io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_) io.host.debug_stats_pcr := io.cpu.map(_.debug_stats_pcr).reduce(_||_)
// system is 'interesting' if any tile is 'interesting' // system is 'interesting' if any tile is 'interesting'