riscv/rocket-chip
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Merge remote-tracking branch 'origin/master' into sim_jtag_reset

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Megan Wachs
2018-03-05 12:41:39 -08:00
parent 5eae81038d 8c6e745653
commit bd3a72e585
66 changed files with 799 additions and 703 deletions
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9
src/main/scala/devices/debug/Periphery.scala
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@ -5,7 +5,7 @@ package freechips.rocketchip.devices.debug
import Chisel._
import chisel3.core.{IntParam, Input, Output}
import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.jtag._
@ -26,12 +26,9 @@ class DebugIO(implicit val p: Parameters) extends ParameterizedBundle()(p) with
/** Either adds a JTAG DTM to system, and exports a JTAG interface,
* or exports the Debug Module Interface (DMI), based on a global parameter.
*/
trait HasPeripheryDebug extends HasPeripheryBus {
val module: HasPeripheryDebugModuleImp
trait HasPeripheryDebug { this: BaseSubsystem =>
val debug = LazyModule(new TLDebugModule(pbus.beatBytes))
debug.node := pbus.toVariableWidthSlaves
pbus.toVariableWidthSlave(Some("debug")){ debug.node }
}
trait HasPeripheryDebugBundle {