can now take interrupts on stalled instructions
This commit is contained in:
Andrew Waterman
parent
2ed0be65f9
commit
bd27d0fab2
@ -358,6 +358,8 @@ class rocketCtrl extends Component
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val ex_reg_inst_di = Reg(resetVal = Bool(false));
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val ex_reg_inst_ei = Reg(resetVal = Bool(false));
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val ex_reg_flush_inst = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_interrupt = Reg(resetVal = Bool(false));
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val ex_reg_cause = Reg(){UFix()}
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val ex_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val ex_reg_xcpt_illegal = Reg(resetVal = Bool(false));
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@ -376,6 +378,8 @@ class rocketCtrl extends Component
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val mem_reg_inst_di = Reg(resetVal = Bool(false));
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val mem_reg_inst_ei = Reg(resetVal = Bool(false));
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val mem_reg_flush_inst = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_interrupt = Reg(resetVal = Bool(false));
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val mem_reg_cause = Reg(){UFix()}
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val mem_reg_xcpt_ma_inst = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_itlb = Reg(resetVal = Bool(false));
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val mem_reg_xcpt_illegal = Reg(resetVal = Bool(false));
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@ -402,7 +406,8 @@ class rocketCtrl extends Component
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val wb_reg_fp_val = Reg(resetVal = Bool(false));
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val wb_reg_fp_sboard_set = Reg(resetVal = Bool(false));
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val take_pc = Wire() { Bool() };
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val take_pc = Wire(){Bool()}
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val take_pc_wb = Wire(){Bool()}
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when (!io.dpath.stalld) {
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when (io.dpath.killf) {
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@ -422,11 +427,46 @@ class rocketCtrl extends Component
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id_reg_icmiss := !io.imem.resp_val;
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}
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var vec_replay = Bool(false)
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var vec_stalld = Bool(false)
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var vec_irq = Bool(false)
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var vec_irq_cause = UFix(23,5) // don't care
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if (HAVE_VEC)
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{
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// vector control
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val vec = new rocketCtrlVec()
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io.vec_dpath <> vec.io.dpath
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io.vec_iface <> vec.io.iface
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vec.io.s := io.dpath.status(SR_S)
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vec.io.sr_ev := io.dpath.status(SR_EV)
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vec.io.exception := wb_reg_exception
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vec.io.eret := wb_reg_eret
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vec_replay = vec.io.replay
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vec_stalld = vec.io.stalld // || id_vfence_cv && !vec.io.vfence_ready
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vec_irq = vec.io.irq
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vec_irq_cause = vec.io.irq_cause
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}
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// executing ERET when traps are enabled causes an illegal instruction exception (as per ISA sim)
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val illegal_inst =
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!(id_int_val.toBool || io.fpu.dec.valid || id_vec_val.toBool) ||
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(id_eret.toBool && io.dpath.status(SR_ET).toBool);
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val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
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val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi);
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val id_interrupt =
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io.dpath.status(SR_ET).toBool && mem_reg_valid &&
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((io.dpath.status(15).toBool && io.dpath.irq_timer) ||
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(io.dpath.status(13).toBool && io.dpath.irq_ipi) ||
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vec_irq);
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val id_cause =
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Mux(p_irq_ipi, UFix(21,5),
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Mux(p_irq_timer, UFix(23,5),
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vec_irq_cause))
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when (reset.toBool || io.dpath.killd) {
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ex_reg_br_type := BR_N;
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ex_reg_btb_hit := Bool(false);
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@ -479,6 +519,8 @@ class rocketCtrl extends Component
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}
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ex_reg_mem_cmd := id_mem_cmd
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ex_reg_mem_type := id_mem_type.toUFix
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ex_reg_xcpt_interrupt := id_reg_valid && id_interrupt && !take_pc
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ex_reg_cause := id_cause
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val beq = io.dpath.br_eq;
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val bne = ~io.dpath.br_eq;
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@ -547,6 +589,8 @@ class rocketCtrl extends Component
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}
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mem_reg_mem_cmd := ex_reg_mem_cmd;
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mem_reg_mem_type := ex_reg_mem_type;
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mem_reg_xcpt_interrupt := ex_reg_xcpt_interrupt && !take_pc_wb
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mem_reg_cause := ex_reg_cause
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when (io.dpath.killm) {
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wb_reg_valid := Bool(false)
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@ -619,82 +663,44 @@ class rocketCtrl extends Component
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io.fpu.dec.wen && fp_sboard.io.r(3).data
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}
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var vec_replay = Bool(false)
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var vec_stalld = Bool(false)
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var vec_irq = Bool(false)
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var vec_irq_cause = UFix(0,5)
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if (HAVE_VEC)
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{
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// vector control
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val vec = new rocketCtrlVec()
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io.vec_dpath <> vec.io.dpath
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io.vec_iface <> vec.io.iface
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vec.io.s := io.dpath.status(SR_S)
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vec.io.sr_ev := io.dpath.status(SR_EV)
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vec.io.exception := wb_reg_exception
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vec.io.eret := wb_reg_eret
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vec_replay = vec.io.replay
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vec_stalld = vec.io.stalld // || id_vfence_cv && !vec.io.vfence_ready
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vec_irq = vec.io.irq
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vec_irq_cause = vec.io.irq_cause
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}
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// exception handling
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// FIXME: verify PC in MEM stage points to valid, restartable instruction
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val p_irq_timer = (io.dpath.status(15).toBool && io.dpath.irq_timer);
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val p_irq_ipi = (io.dpath.status(13).toBool && io.dpath.irq_ipi);
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val interrupt =
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io.dpath.status(SR_ET).toBool && mem_reg_valid &&
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((io.dpath.status(15).toBool && io.dpath.irq_timer) ||
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(io.dpath.status(13).toBool && io.dpath.irq_ipi) ||
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vec_irq);
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val interrupt_cause =
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Mux(p_irq_ipi, UFix(21,5),
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Mux(p_irq_timer, UFix(23,5),
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Mux(vec_irq, vec_irq_cause,
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UFix(0,5))))
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val mem_xcpt_ma_ld = io.dmem.xcpt_ma_ld && !mem_reg_kill
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val mem_xcpt_ma_st = io.dmem.xcpt_ma_st && !mem_reg_kill
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val mem_xcpt_dtlb_ld = io.xcpt_dtlb_ld && !mem_reg_kill
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val mem_xcpt_dtlb_st = io.xcpt_dtlb_st && !mem_reg_kill
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val mem_exception =
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interrupt ||
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mem_xcpt_ma_ld ||
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mem_xcpt_ma_st ||
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mem_xcpt_dtlb_ld ||
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mem_xcpt_dtlb_st ||
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mem_reg_xcpt_illegal ||
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mem_reg_xcpt_privileged ||
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mem_reg_xcpt_fpu ||
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mem_reg_xcpt_vec ||
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mem_reg_xcpt_syscall ||
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mem_reg_xcpt_itlb ||
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mem_reg_xcpt_ma_inst;
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val mem_exception =
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mem_reg_xcpt_interrupt ||
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mem_xcpt_ma_ld ||
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mem_xcpt_ma_st ||
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mem_xcpt_dtlb_ld ||
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mem_xcpt_dtlb_st ||
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mem_reg_xcpt_illegal ||
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mem_reg_xcpt_privileged ||
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mem_reg_xcpt_fpu ||
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mem_reg_xcpt_vec ||
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mem_reg_xcpt_syscall ||
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mem_reg_xcpt_itlb ||
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mem_reg_xcpt_ma_inst;
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val mem_cause =
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Mux(interrupt, interrupt_cause, // asynchronous interrupt
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Mux(mem_reg_xcpt_itlb, UFix(1,5), // instruction access fault
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Mux(mem_reg_xcpt_illegal, UFix(2,5), // illegal instruction
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Mux(mem_reg_xcpt_privileged, UFix(3,5), // privileged instruction
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Mux(mem_reg_xcpt_fpu, UFix(4,5), // FPU disabled
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Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
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// breakpoint
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Mux(mem_xcpt_ma_ld, UFix(8,5), // misaligned load
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Mux(mem_xcpt_ma_st, UFix(9,5), // misaligned store
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Mux(mem_xcpt_dtlb_ld, UFix(10,5), // load fault
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Mux(mem_xcpt_dtlb_st, UFix(11,5), // store fault
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Mux(mem_reg_xcpt_vec, UFix(12,5), // vector disabled
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UFix(0,5)))))))))))); // instruction address misaligned
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val mem_cause =
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Mux(mem_reg_xcpt_interrupt, mem_reg_cause, // asynchronous interrupt
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Mux(mem_reg_xcpt_itlb, UFix(1,5), // instruction access fault
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Mux(mem_reg_xcpt_illegal, UFix(2,5), // illegal instruction
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Mux(mem_reg_xcpt_privileged, UFix(3,5), // privileged instruction
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Mux(mem_reg_xcpt_fpu, UFix(4,5), // FPU disabled
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Mux(mem_reg_xcpt_syscall, UFix(6,5), // system call
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// breakpoint
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Mux(mem_xcpt_ma_ld, UFix(8,5), // misaligned load
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Mux(mem_xcpt_ma_st, UFix(9,5), // misaligned store
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Mux(mem_xcpt_dtlb_ld, UFix(10,5), // load fault
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Mux(mem_xcpt_dtlb_st, UFix(11,5), // store fault
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Mux(mem_reg_xcpt_vec, UFix(12,5), // vector disabled
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UFix(0,5)))))))))))); // instruction address misaligned
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// control transfer from ex/mem
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val take_pc_ex = ex_reg_btb_hit != br_taken || jr_taken
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val take_pc_wb = wb_reg_replay || vec_replay || wb_reg_exception || wb_reg_eret
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take_pc_wb := wb_reg_replay || vec_replay || wb_reg_exception || wb_reg_eret
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take_pc := take_pc_ex || take_pc_wb;
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// replay mem stage PC on a DTLB miss or a long-latency writeback
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