From bd241ea2375cffb1c1db05b176f200895ad9f2a0 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Mon, 30 Jan 2012 17:15:42 -0800 Subject: [PATCH] fix when badvaddr is set --- rocket/src/main/scala/ctrl.scala | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/rocket/src/main/scala/ctrl.scala b/rocket/src/main/scala/ctrl.scala index 74c6ef41..3dbbb11e 100644 --- a/rocket/src/main/scala/ctrl.scala +++ b/rocket/src/main/scala/ctrl.scala @@ -362,7 +362,6 @@ class rocketCtrl extends Component val wb_reg_flush_inst = Reg(resetVal = Bool(false)); val wb_reg_eret = Reg(resetVal = Bool(false)); val wb_reg_exception = Reg(resetVal = Bool(false)); - val wb_reg_badvaddr_wen = Reg(resetVal = Bool(false)); val wb_reg_replay = Reg(resetVal = Bool(false)); val wb_reg_cause = Reg(){UFix()}; @@ -549,11 +548,6 @@ class rocketCtrl extends Component Mux(mem_xcpt_dtlb_st, UFix(11,5), // store fault UFix(0,5))))))))))); // instruction address misaligned - // write cause to PCR on an exception - io.dpath.exception := wb_reg_exception; - io.dpath.cause := wb_reg_cause; - io.dpath.badvaddr_wen := wb_reg_badvaddr_wen; - // control transfer from ex/mem val ex_btb_match = ex_reg_btb_hit && io.dpath.btb_match val br_jr_taken = br_taken || jr_taken @@ -577,9 +571,15 @@ class rocketCtrl extends Component wb_reg_replay <== replay_mem && !take_pc_wb; wb_reg_exception <== mem_exception && !take_pc_wb; - wb_reg_badvaddr_wen <== (mem_xcpt_dtlb_ld || mem_xcpt_dtlb_st) && !take_pc_wb; wb_reg_cause <== mem_cause; + val wb_badvaddr_wen = wb_reg_exception && ((wb_reg_cause === UFix(10)) || (wb_reg_cause === UFix(11))) + + // write cause to PCR on an exception + io.dpath.exception := wb_reg_exception; + io.dpath.cause := wb_reg_cause; + io.dpath.badvaddr_wen := wb_badvaddr_wen; + io.dpath.sel_pc := Mux(wb_reg_exception, PC_EVEC, // exception Mux(wb_reg_replay, PC_WB, // replay