From bc39d52655da813d23387509f39aaa3ba5a9e5aa Mon Sep 17 00:00:00 2001 From: Howard Mao Date: Mon, 18 Jul 2016 18:26:18 -0700 Subject: [PATCH] changes to multi-transaction timer --- groundtest/src/main/scala/Comparator.scala | 4 ++-- groundtest/src/main/scala/NastiTest.scala | 8 ++++---- groundtest/src/main/scala/TraceGen.scala | 22 +++++++++++---------- groundtest/src/main/scala/common/Util.scala | 12 +++++++---- 4 files changed, 26 insertions(+), 20 deletions(-) diff --git a/groundtest/src/main/scala/Comparator.scala b/groundtest/src/main/scala/Comparator.scala index 821cb931..7643418a 100644 --- a/groundtest/src/main/scala/Comparator.scala +++ b/groundtest/src/main/scala/Comparator.scala @@ -300,8 +300,8 @@ class ComparatorClient(val target: Long)(implicit val p: Parameters) extends Mod timer.io.start.bits := xact_id timer.io.stop.valid := io.tl.grant.fire() && io.tl.grant.bits.first() timer.io.stop.bits := io.tl.grant.bits.client_xact_id - assert(!timer.io.timeout, "Comparator TL client timed out") - io.timeout := timer.io.timeout + assert(!timer.io.timeout.valid, "Comparator TL client timed out") + io.timeout := timer.io.timeout.valid } class ComparatorSink(implicit val p: Parameters) extends Module diff --git a/groundtest/src/main/scala/NastiTest.scala b/groundtest/src/main/scala/NastiTest.scala index a665616c..c12a0c76 100644 --- a/groundtest/src/main/scala/NastiTest.scala +++ b/groundtest/src/main/scala/NastiTest.scala @@ -91,17 +91,17 @@ class NastiGenerator(id: Int)(implicit val p: Parameters) extends Module r_timer.io.start.bits := io.mem.ar.bits.id r_timer.io.stop.valid := io.mem.r.fire() && io.mem.r.bits.last r_timer.io.stop.bits := io.mem.r.bits.id - assert(!r_timer.io.timeout, "NASTI Read timed out") + assert(!r_timer.io.timeout.valid, "NASTI Read timed out") val w_timer = Module(new Timer(1000, 2)) w_timer.io.start.valid := io.mem.aw.fire() w_timer.io.start.bits := io.mem.aw.bits.id w_timer.io.stop.valid := io.mem.b.fire() w_timer.io.stop.bits := io.mem.b.bits.id - assert(!w_timer.io.timeout, "NASTI Write timed out") + assert(!w_timer.io.timeout.valid, "NASTI Write timed out") - io.status.timeout.valid := r_timer.io.timeout || w_timer.io.timeout - io.status.timeout.bits := Mux(r_timer.io.timeout, UInt(1), UInt(2)) + io.status.timeout.valid := r_timer.io.timeout.valid || w_timer.io.timeout.valid + io.status.timeout.bits := Mux(r_timer.io.timeout.valid, UInt(1), UInt(2)) } class NastiConverterTest(implicit p: Parameters) extends GroundTest()(p) diff --git a/groundtest/src/main/scala/TraceGen.scala b/groundtest/src/main/scala/TraceGen.scala index b2d4f93d..ba62ae33 100644 --- a/groundtest/src/main/scala/TraceGen.scala +++ b/groundtest/src/main/scala/TraceGen.scala @@ -73,6 +73,7 @@ trait HasTraceGenParams { val genExtraAddrs = false val logNumExtraAddrs = 1 val numExtraAddrs = 1 << logNumExtraAddrs + val maxTags = 8 require(numBytesInWord * 8 == numBitsInWord) require((1 << logAddressBagLen) == addressBagLen) @@ -183,6 +184,14 @@ class TraceGenerator(id: Int) val mem = new HellaCacheIO } + val reqTimer = Module(new Timer(8192, maxTags)) + reqTimer.io.start.valid := io.mem.req.fire() + reqTimer.io.start.bits := io.mem.req.bits.tag + reqTimer.io.stop.valid := io.mem.resp.valid + reqTimer.io.stop.bits := io.mem.resp.bits.tag + + assert(!reqTimer.io.timeout.valid, s"TraceGen core ${id}: request timed out") + // Random addresses // ---------------- @@ -264,7 +273,7 @@ class TraceGenerator(id: Int) // "tag", used to match each response with its corresponding request. // Create a tag manager giving out unique 3-bit tags - val tagMan = Module(new TagMan(3)) + val tagMan = Module(new TagMan(log2Ceil(maxTags))) // Default inputs tagMan.io.take := Bool(false); @@ -455,7 +464,7 @@ class TraceGenerator(id: Int) when (sendFreshReq) { // Grab a unique tag for the request - reqTag := Cat(UInt(0), tagMan.io.tagOut) + reqTag := tagMan.io.tagOut tagMan.io.take := Bool(true) // Fill in unique data reqData := Cat(nextData, tid) @@ -521,13 +530,6 @@ class TraceGenerator(id: Int) respCount := respCount + UInt(1) } - // Response timeouts - // --------------------------- - - // Raise an error if a response takes too long to come back - val timeout = Timer(memRespTimeout, sendFreshReq, io.mem.resp.valid) - assert(!timeout, s"Core ${id}: response timeout") - // Termination condition // --------------------- @@ -542,7 +544,7 @@ class TraceGenerator(id: Int) } io.finished := Bool(false) - io.timeout := timeout + io.timeout := reqTimer.io.timeout.valid } // ======================= diff --git a/groundtest/src/main/scala/common/Util.scala b/groundtest/src/main/scala/common/Util.scala index 219eafd3..e8e28e20 100644 --- a/groundtest/src/main/scala/common/Util.scala +++ b/groundtest/src/main/scala/common/Util.scala @@ -8,13 +8,13 @@ import Chisel._ // Timer with a statically-specified period. // Can take multiple inflight start-stop events with ID -// Will continue to count down so long as at least one inflight event +// Will continue to count down as long as at least one event is inflight class Timer(initCount: Int, maxInflight: Int) extends Module { val io = new Bundle { val start = Valid(UInt(width = log2Up(maxInflight))).flip val stop = Valid(UInt(width = log2Up(maxInflight))).flip - val timeout = Bool(OUTPUT) + val timeout = Valid(UInt(width = log2Up(maxInflight))) } val inflight = Reg(init = Vec.fill(maxInflight) { Bool(false) }) @@ -33,7 +33,11 @@ class Timer(initCount: Int, maxInflight: Int) extends Module { inflight(io.stop.bits) := Bool(false) } - io.timeout := countdown === UInt(0) && active + io.timeout.valid := countdown === UInt(0) && active + io.timeout.bits := PriorityEncoder(inflight) + + assert(!io.stop.valid || inflight(io.stop.bits), + "Timer stop for transaction that's not inflight") } object Timer { @@ -43,7 +47,7 @@ object Timer { timer.io.start.bits := UInt(0) timer.io.stop.valid := stop timer.io.stop.bits := UInt(0) - timer.io.timeout + timer.io.timeout.valid } }