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diplomacy: place Monitors inside LazyModules sinks

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We used to place Monitors at the point of the ':='.
This was problematic because the clock domain might be wrong.
Thus, we needed to shove Monitors a lot.

Furthermore, now that we have cross-module ':=', you might not even
have access to the wires at the point where ':=' is invoked.
This commit is contained in:
Wesley W. Terpstra
2017-09-22 16:55:12 -07:00
parent cfb7f13408
commit bc225a4e82
7 changed files with 41 additions and 105 deletions
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20
src/main/scala/tilelink/Monitor.scala
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@ -8,26 +8,22 @@ import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.util.{HeterogeneousBag, PlusArg}
case class TLMonitorArgs(edge: () => Seq[TLEdge], sourceInfo: SourceInfo, p: Parameters)
case class TLMonitorArgs(edge: TLEdge)
abstract class TLMonitorBase(args: TLMonitorArgs) extends MonitorBase()(args.sourceInfo, args.p)
abstract class TLMonitorBase(args: TLMonitorArgs) extends Module
{
def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool): Unit
lazy val module = new LazyModuleImp(this) {
val edges = args.edge()
val io = IO(new Bundle {
val in = HeterogeneousBag(edges.map(p => new TLBundleSnoop(p.bundle))).flip
})
(edges zip io.in).foreach { case (e, in) => legalize(in, e, reset) }
val io = new Bundle {
val in = new TLBundleSnoop(args.edge.bundle).flip
}
def legalize(bundle: TLBundleSnoop, edge: TLEdge, reset: Bool): Unit
legalize(io.in, args.edge, reset)
}
class TLMonitor(args: TLMonitorArgs) extends TLMonitorBase(args)
{
def extra = {
sourceInfo match {
args.edge.sourceInfo match {
case SourceLine(filename, line, col) => s" (connected at $filename:$line:$col)"
case _ => ""
}