riscv/rocket-chip
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WIP on priv spec v1.9

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This commit is contained in:
Andrew Waterman
2016-03-02 23:29:58 -08:00
parent 091782ad27
commit bc15e8649e
10 changed files with 316 additions and 300 deletions
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37
rocket/src/main/scala/tlb.scala
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@ -100,7 +100,6 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val tag_hit_addr = OHToUInt(tag_cam.io.hits)
// permission bit arrays
val valid_array = Reg(Vec(entries, Bool())) // PTE is valid (not equivalent to CAM tag valid bit!)
val ur_array = Reg(Vec(entries, Bool())) // user read permission
val uw_array = Reg(Vec(entries, Bool())) // user write permission
val ux_array = Reg(Vec(entries, Bool())) // user execute permission
@ -111,13 +110,12 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
when (io.ptw.resp.valid) {
val pte = io.ptw.resp.bits.pte
tag_ram(r_refill_waddr) := pte.ppn
valid_array(r_refill_waddr) := !io.ptw.resp.bits.error
ur_array(r_refill_waddr) := pte.ur() && !io.ptw.resp.bits.error
uw_array(r_refill_waddr) := pte.uw() && !io.ptw.resp.bits.error
ux_array(r_refill_waddr) := pte.ux() && !io.ptw.resp.bits.error
sr_array(r_refill_waddr) := pte.sr() && !io.ptw.resp.bits.error
sw_array(r_refill_waddr) := pte.sw() && !io.ptw.resp.bits.error
sx_array(r_refill_waddr) := pte.sx() && !io.ptw.resp.bits.error
ur_array(r_refill_waddr) := pte.ur()
uw_array(r_refill_waddr) := pte.uw()
ux_array(r_refill_waddr) := pte.ux()
sr_array(r_refill_waddr) := pte.sr()
sw_array(r_refill_waddr) := pte.sw()
sx_array(r_refill_waddr) := pte.sx()
dirty_array(r_refill_waddr) := pte.d
}
@ -126,14 +124,17 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
val invalid_entry = PriorityEncoder(~tag_cam.io.valid_bits)
val plru = new PseudoLRU(entries)
val repl_waddr = Mux(has_invalid_entry, invalid_entry, plru.replace)
val priv = Mux(io.ptw.status.mprv && !io.req.bits.instruction, io.ptw.status.prv1, io.ptw.status.prv)
val priv_s = priv === PRV_S
val priv_uses_vm = priv <= PRV_S
val do_mprv = io.ptw.status.prv === PRV.M && io.ptw.status.mprv && !io.req.bits.instruction
val priv = Mux(do_mprv, io.ptw.status.mpp, io.ptw.status.prv)
val priv_s = priv === PRV.S
val priv_uses_vm = priv <= PRV.S
val req_xwr = Cat(!r_req.store, r_req.store, !(r_req.instruction || r_req.store))
val r_array = Mux(priv_s, sr_array.toBits, ur_array.toBits)
val w_array = Mux(priv_s, sw_array.toBits, uw_array.toBits)
val ur_bits = ur_array.toBits
val pum_ok = ~Mux(io.ptw.status.pum, ur_bits, UInt(0))
val r_array = Mux(priv_s, sr_array.toBits & pum_ok, ur_bits)
val w_array = Mux(priv_s, sw_array.toBits & pum_ok, uw_array.toBits)
val x_array = Mux(priv_s, sx_array.toBits, ux_array.toBits)
val vm_enabled = io.ptw.status.vm(3) && priv_uses_vm && !io.req.bits.passthrough
@ -160,10 +161,10 @@ class TLB(implicit p: Parameters) extends TLBModule()(p) {
io.resp.ppn := Mux(vm_enabled, Mux1H(tag_cam.io.hits, tag_ram), io.req.bits.vpn(ppnBits-1,0))
io.resp.hit_idx := tag_cam.io.hits
// clear invalid entries on access, or all entries on a TLB flush
tag_cam.io.clear := io.ptw.invalidate || io.req.fire()
tag_cam.io.clear_mask := ~valid_array.toBits | (tag_cam.io.hits & ~tag_hits)
when (io.ptw.invalidate) { tag_cam.io.clear_mask := ~UInt(0, entries) }
// clear entries on a TLB flush.
// TODO: selective flushing. careful with superpage mappings (flush it all)
tag_cam.io.clear := io.ptw.invalidate
tag_cam.io.clear_mask := ~UInt(0, entries)
io.ptw.req.valid := state === s_request
io.ptw.req.bits.addr := r_refill_tag