riscv/rocket-chip
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WIP on priv spec v1.9

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This commit is contained in:
Andrew Waterman
2016-03-02 23:29:58 -08:00
parent 091782ad27
commit bc15e8649e
10 changed files with 316 additions and 300 deletions
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2
rocket/src/main/scala/tile.scala
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@ -84,7 +84,7 @@ class RocketTile(resetSignal: Bool = null)(implicit p: Parameters) extends Tile(
}))
val dcIF = Module(new SimpleHellaCacheIF()(dcacheParams))
rocc.io.cmd <> cmdRouter.io.out(i)
rocc.io.s := core.io.rocc.s
rocc.io.status := core.io.rocc.status
rocc.io.exception := core.io.rocc.exception
rocc.io.host_id := io.host.id
dcIF.io.requestor <> rocc.io.mem