riscv/rocket-chip
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Tests: include more random delays

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This commit is contained in:
Wesley W. Terpstra 2017-03-10 17:10:41 -08:00
parent 0c7fb87390
commit bb6108abd5
11 changed files with 19 additions and 19 deletions
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2
src/main/scala/uncore/ahb/Test.scala
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@ -25,7 +25,7 @@ class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
val gpio = LazyModule(new RRTest0(0x100)) val gpio = LazyModule(new RRTest0(0x100))
model.node := fuzz.node model.node := fuzz.node
xbar.node := TLToAHB()(model.node) xbar.node := TLToAHB()(TLDelayer(0.1)(model.node))
ram.node := xbar.node ram.node := xbar.node
gpio.node := xbar.node gpio.node := xbar.node

2
src/main/scala/uncore/apb/Test.scala
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@ -25,7 +25,7 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule
val gpio = LazyModule(new RRTest0(0x100)) val gpio = LazyModule(new RRTest0(0x100))
model.node := fuzz.node model.node := fuzz.node
xbar.node := TLToAPB()(model.node) xbar.node := TLToAPB()(TLDelayer(0.1)(model.node))
ram.node := xbar.node ram.node := xbar.node
gpio.node := xbar.node gpio.node := xbar.node

6
src/main/scala/uncore/axi4/Test.scala
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@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node model.node := fuzz.node
xbar.node := model.node xbar.node := TLDelayer(0.1)(model.node)
ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node)) ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node)) gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node model.node := fuzz.node
xbar.node := model.node xbar.node := TLDelayer(0.1)(model.node)
ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node)) ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node)) gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
@ -69,7 +69,7 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
val model = LazyModule(new TLRAMModel("AXI4FuzzMaster")) val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
model.node := fuzz.node model.node := fuzz.node
node := TLToAXI4(4)(model.node) node := TLToAXI4(4)(TLDelayer(0.1)(model.node))
lazy val module = new LazyModuleImp(this) { lazy val module = new LazyModuleImp(this) {
val io = new Bundle { val io = new Bundle {

2
src/main/scala/uncore/tilelink2/AsyncCrossing.scala
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@ -144,7 +144,7 @@ class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule {
val cross = LazyModule(new TLAsyncCrossing) val cross = LazyModule(new TLAsyncCrossing)
model.node := fuzz.node model.node := fuzz.node
cross.node := TLFragmenter(4, 256)(model.node) cross.node := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node))
val monitor = (ram.node := cross.node) val monitor = (ram.node := cross.node)
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {

2
src/main/scala/uncore/tilelink2/AtomicAutomata.scala
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@ -299,7 +299,7 @@ class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule {
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node model.node := fuzz.node
ram.node := TLFragmenter(4, 256)(TLAtomicAutomata()(model.node)) ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node))))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

2
src/main/scala/uncore/tilelink2/Fragmenter.scala
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@ -267,7 +267,7 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) e
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node model.node := fuzz.node
ram.node := TLFragmenter(ramBeatBytes, maxSize)(model.node) ram.node := TLDelayer(0.1)(TLFragmenter(ramBeatBytes, maxSize)(TLDelayer(0.1)(model.node)))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

2
src/main/scala/uncore/tilelink2/HintHandler.scala
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@ -116,7 +116,7 @@ class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule {
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node model.node := fuzz.node
ram.node := TLFragmenter(4, 256)(TLHintHandler()(model.node)) ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node))))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

4
src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
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@ -259,7 +259,7 @@ class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
val rrtr = LazyModule(new RRTest0(0x400)) val rrtr = LazyModule(new RRTest0(0x400))
rrtr.node := TLFragmenter(4, 32)(TLBuffer()(fuzz.node)) rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished
@ -274,7 +274,7 @@ class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
val rrtr = LazyModule(new RRTest1(0x400)) val rrtr = LazyModule(new RRTest1(0x400))
rrtr.node := TLFragmenter(4, 32)(TLBuffer()(fuzz.node)) rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

2
src/main/scala/uncore/tilelink2/SRAM.scala
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@ -95,7 +95,7 @@ class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes))
model.node := fuzz.node model.node := fuzz.node
ram.node := model.node ram.node := TLDelayer(0.25)(model.node)
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

6
src/main/scala/uncore/tilelink2/WidthWidget.scala
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@ -180,11 +180,11 @@ class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node model.node := fuzz.node
ram.node := TLFragmenter(4, 256)( ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)(
if (first == second ) { TLWidthWidget(first)(model.node) } if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) }
else { else {
TLWidthWidget(second)( TLWidthWidget(second)(
TLWidthWidget(first)(model.node))}) TLWidthWidget(first)(TLDelayer(0.1)(model.node)))}))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished io.finished := fuzz.module.io.finished

8
src/main/scala/uncore/tilelink2/Xbar.scala
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@ -191,10 +191,10 @@ class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule {
val xbar = LazyModule(new TLXbar) val xbar = LazyModule(new TLXbar)
model.node := fuzz.node model.node := fuzz.node
xbar.node := model.node xbar.node := TLDelayer(0.1)(model.node)
(0 until nManagers) foreach { n => (0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256)(xbar.node) ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
} }
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
@ -211,13 +211,13 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) e
val fuzzers = (0 until nClients) map { n => val fuzzers = (0 until nClients) map { n =>
val fuzz = LazyModule(new TLFuzzer(5000)) val fuzz = LazyModule(new TLFuzzer(5000))
xbar.node := fuzz.node xbar.node := TLDelayer(0.1)(fuzz.node)
fuzz fuzz
} }
(0 until nManagers) foreach { n => (0 until nManagers) foreach { n =>
val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff)))
ram.node := TLFragmenter(4, 256)(xbar.node) ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node))
} }
lazy val module = new LazyModuleImp(this) with HasUnitTestIO { lazy val module = new LazyModuleImp(this) with HasUnitTestIO {