riscv/rocket-chip
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Tests: include more random delays

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This commit is contained in:
Wesley W. Terpstra
2017-03-10 17:10:41 -08:00
parent 0c7fb87390
commit bb6108abd5
11 changed files with 19 additions and 19 deletions
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6
src/main/scala/uncore/tilelink2/WidthWidget.scala
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@ -180,11 +180,11 @@ class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends
val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node
ram.node := TLFragmenter(4, 256)(
if (first == second ) { TLWidthWidget(first)(model.node) }
ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)(
if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) }
else {
TLWidthWidget(second)(
TLWidthWidget(first)(model.node))})
TLWidthWidget(first)(TLDelayer(0.1)(model.node)))}))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished