riscv/rocket-chip
1
0 Fork 0
Code Releases Activity

Tests: include more random delays

Browse Source
This commit is contained in:
Wesley W. Terpstra committed 2017-03-11 02:53:43 -08:00
1 parent 0c7fb87390
commit bb6108abd5
11 files changed
+19 -19
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

src/main/scala/uncore/tilelink2/RegisterRouterTest.scala
+2 -2
View File
@@ -259,7 +259,7 @@ class FuzzRRTest0()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val rrtr = LazyModule(new RRTest0(0x400))
rrtr.node := TLFragmenter(4, 32)(TLBuffer()(fuzz.node))
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished
@@ -274,7 +274,7 @@ class FuzzRRTest1()(implicit p: Parameters) extends LazyModule {
val fuzz = LazyModule(new TLFuzzer(5000))
val rrtr = LazyModule(new RRTest1(0x400))
rrtr.node := TLFragmenter(4, 32)(TLBuffer()(fuzz.node))
rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node))
lazy val module = new LazyModuleImp(this) with HasUnitTestIO {
io.finished := fuzz.module.io.finished