riscv/rocket-chip
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Tests: include more random delays

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This commit is contained in:
Wesley W. Terpstra
2017-03-10 17:10:41 -08:00
parent 0c7fb87390
commit bb6108abd5
11 changed files with 19 additions and 19 deletions
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6
src/main/scala/uncore/axi4/Test.scala
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@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node
xbar.node := model.node
xbar.node := TLDelayer(0.1)(model.node)
ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node))
gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node))
@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule
val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff)))
model.node := fuzz.node
xbar.node := model.node
xbar.node := TLDelayer(0.1)(model.node)
ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node))
gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node))
@ -69,7 +69,7 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule
val model = LazyModule(new TLRAMModel("AXI4FuzzMaster"))
model.node := fuzz.node
node := TLToAXI4(4)(model.node)
node := TLToAXI4(4)(TLDelayer(0.1)(model.node))
lazy val module = new LazyModuleImp(this) {
val io = new Bundle {