riscv/rocket-chip
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Tests: include more random delays

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Wesley W. Terpstra committed 2017-03-11 02:53:43 -08:00
1 parent 0c7fb87390
commit bb6108abd5
11 files changed
+19 -19
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src/main/scala/uncore/ahb/Test.scala
+1 -1
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@@ -25,7 +25,7 @@ class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule
val gpio = LazyModule(new RRTest0(0x100))
model.node := fuzz.node
xbar.node := TLToAHB()(model.node)
xbar.node := TLToAHB()(TLDelayer(0.1)(model.node))
ram.node := xbar.node
gpio.node := xbar.node