From bb5c465bb35601fb4fcdcec106b13aa175816a2f Mon Sep 17 00:00:00 2001 From: Henry Cook Date: Tue, 22 Jan 2013 19:57:31 -0800 Subject: [PATCH] Switched back to old, better-tested hub on master --- src/main/scala/RocketChip.scala | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/main/scala/RocketChip.scala b/src/main/scala/RocketChip.scala index 78d4dbbc..5b1c1167 100644 --- a/src/main/scala/RocketChip.scala +++ b/src/main/scala/RocketChip.scala @@ -221,19 +221,21 @@ class OuterMemorySystem(htif_width: Int, tileEndpoints: Seq[ClientCoherenceAgent val llc = new DRAMSideLLC(512, 8, 4, llc_tag_leaf, llc_data_leaf) val mem_serdes = new MemSerdes(htif_width) - //val hub = new CoherenceHubBroadcast()(chWithHtifConf) + val hub = new CoherenceHubBroadcast()(chWithHtifConf) //val adapter = new CoherenceHubAdapter()(lnWithHtifConf) - val hub = new L2CoherenceAgent()(chWithHtifConf) - val net = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)(lnWithHtifConf) + //val hub = new L2CoherenceAgent()(chWithHtifConf) + //val net = new ReferenceChipCrossbarNetwork(List(hub)++tileEndpoints)(lnWithHtifConf) //net.io(0) <> adapter.io.net //hub.io.tiles <> adapter.io.hub - hub.io.network <> net.io(0) + //hub.io.network <> net.io(0) for (i <- 1 to conf.ln.nTiles) { - net.io(i) <> io.tiles(i-1) + //net.io(i) <> io.tiles(i-1) + hub.io.tiles(i-1) <> io.tiles(i-1) hub.io.incoherent(i-1) := io.incoherent(i-1) } - net.io(conf.ln.nTiles+1) <> io.htif + //net.io(conf.ln.nTiles+1) <> io.htif + hub.io.tiles(conf.ln.nTiles) <> io.htif hub.io.incoherent(conf.ln.nTiles) := Bool(true) llc.io.cpu.req_cmd <> Queue(hub.io.mem.req_cmd)