now able to add periphery devices through traits
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits. This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
This commit is contained in:
Yunsup Lee
@ -8,6 +8,7 @@ import rocket._
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import rocket.Util._
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import uncore.agents._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule}
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import uncore.devices._
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import uncore.converters._
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import coreplex._
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@ -17,156 +18,66 @@ import scala.collection.immutable.HashMap
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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class BasePlatformConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val internalIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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if (site(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
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require(site(NTiles) == 1) // TODO relax this
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require(site(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM
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entries += AddrMapEntry("dmem0", MemRange(0x80000000L, site[Int](DataScratchpadSize), MemAttr(AddrMapProt.RWX)))
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}
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new AddrMap(entries)
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}
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lazy val externalAddrMap = new AddrMap(
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site(ExtraDevices).addrMapEntries ++ site(ExtMMIOPorts),
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start = BigInt("50000000", 16),
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collapse = true)
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = site(ExtMemSize)
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val intern = AddrMapEntry("int", internalIOAddrMap)
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val extern = AddrMapEntry("ext", externalAddrMap)
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val io = AddrMapEntry("io", AddrMap((intern +: site(ExportMMIOPort).option(extern).toSeq):_*))
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val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
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val addrMap = AddrMap((io +: (site(NMemoryChannels) > 0).option(mem).toSeq):_*)
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Dump("MEM_BASE", memBase)
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addrMap
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}
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def makeConfigString() = {
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val addrMap = globalAddrMap
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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val plicInfo = site(PLICKey)
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val xLen = site(XLen)
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val res = new StringBuilder
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
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res append s" ndevs ${plicInfo.nDevices};\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
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res append "};\n"
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if (addrMap contains "mem") {
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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}
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res append "core {\n"
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for (i <- 0 until site(NTiles)) { // TODO heterogeneous tiles
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val isa = {
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val m = if (site(MulDivKey).nonEmpty) "m" else ""
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val a = if (site(UseAtomics)) "a" else ""
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val f = if (site(FPUKey).nonEmpty) "f" else ""
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val d = if (site(FPUKey).nonEmpty && site(XLen) > 32) "d" else ""
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val s = if (site(UseVM)) "s" else ""
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s"rv${site(XLen)}i$m$a$f$d$s"
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class BasePlatformConfig extends Config(
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topDefinitions = {
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val configString = new GlobalVariable[String]
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val globalAddrMap = new GlobalVariable[AddrMap]
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val nCoreplexExtClients = new GlobalVariable[Int]
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(pname,site,here) => {
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
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res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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if (site(UseVM)) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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res append " };\n"
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res append " };\n"
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res append " };\n"
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case BuildCoreplex =>
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(p: Parameters, c: CoreplexConfig) => Module(new DefaultCoreplex(p, c))
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case NExtTopInterrupts => 2
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// Note that PLIC asserts that this is > 0.
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncMMIOChannels => false
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case ExtMMIOPorts => Nil
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NCoreplexExtClients => nCoreplexExtClients
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => configString
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case GlobalAddrMap => globalAddrMap
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case BuildExampleTop =>
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(p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTop(p))
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case _ => throw new CDEMatchError
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}
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res append "};\n"
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res append (site(ExtraDevices).makeConfigString(addrMap))
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res append '\u0000'
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res.toString.getBytes
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}
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
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case NExtTopInterrupts => 2
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case NExtPeripheryInterrupts => site(ExtraDevices).nInterrupts
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// Note that PLIC asserts that this is > 0.
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case NExtInterrupts => site(NExtTopInterrupts) + site(NExtPeripheryInterrupts)
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncMMIOChannels => false
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case ExtraDevices => new EmptyDeviceBlock
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case ExtraTopPorts => (p: Parameters) => new Bundle
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case ExtMMIOPorts => Nil
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case ExportMMIOPort => !externalAddrMap.isEmpty
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +
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site(ExtraDevices).nClientPorts
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case ConnectExtraPorts =>
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(out: Bundle, in: Bundle, p: Parameters) => out <> in
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case _ => throw new CDEMatchError
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}})
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})
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class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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@ -178,7 +89,6 @@ class DefaultBufferlessConfig extends Config(
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class FPGAConfig extends Config (
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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case ExportGroundTestStatus => true
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case _ => throw new CDEMatchError
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}
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)
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@ -269,35 +179,12 @@ class TinyConfig extends Config(
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new WithSmallCores ++ new WithRV32 ++
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new WithStatelessBridge ++ new BaseConfig)
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class WithTestRAM extends Config(
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(pname, site, here) => pname match {
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case ExtraDevices => {
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class TestRAMDevice extends DeviceBlock {
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val ramSize = 0x1000
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def nClientPorts = 0
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def addrMapEntries = Seq(
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AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))))
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def builder(
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mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
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clientPorts: Seq[ClientUncachedTileLinkIO],
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interrupts: Seq[Bool],
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extra: Bundle, p: Parameters) {
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val testram = Module(new TileLinkTestRAM(ramSize)(p))
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testram.io <> mmioPorts("testram")
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}
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}
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new TestRAMDevice
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}
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}
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)
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class WithAsyncDebug extends Config (
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(pname, site, here) => pname match {
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case AsyncDebugBus => true
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}
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)
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class WithJtagDTM extends Config (
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(pname, site, here) => pname match {
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case IncludeJtagDTM => true
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