now able to add periphery devices through traits
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits. This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
This commit is contained in:
Yunsup Lee
@ -8,6 +8,7 @@ import rocket._
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import rocket.Util._
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import uncore.agents._
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import uncore.tilelink._
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import uncore.tilelink2.{LazyModule}
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import uncore.devices._
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import uncore.converters._
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import coreplex._
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@ -17,156 +18,66 @@ import scala.collection.immutable.HashMap
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import DefaultTestSuites._
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import cde.{Parameters, Config, Dump, Knob, CDEMatchError}
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class BasePlatformConfig extends Config (
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topDefinitions = { (pname,site,here) =>
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val internalIOAddrMap: AddrMap = {
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val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
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entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
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entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
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entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
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entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
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if (site(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
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require(site(NTiles) == 1) // TODO relax this
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require(site(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM
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entries += AddrMapEntry("dmem0", MemRange(0x80000000L, site[Int](DataScratchpadSize), MemAttr(AddrMapProt.RWX)))
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}
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new AddrMap(entries)
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}
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lazy val externalAddrMap = new AddrMap(
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site(ExtraDevices).addrMapEntries ++ site(ExtMMIOPorts),
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start = BigInt("50000000", 16),
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collapse = true)
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lazy val globalAddrMap = {
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val memBase = 0x80000000L
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val memSize = site(ExtMemSize)
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val intern = AddrMapEntry("int", internalIOAddrMap)
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val extern = AddrMapEntry("ext", externalAddrMap)
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val io = AddrMapEntry("io", AddrMap((intern +: site(ExportMMIOPort).option(extern).toSeq):_*))
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val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
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val addrMap = AddrMap((io +: (site(NMemoryChannels) > 0).option(mem).toSeq):_*)
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Dump("MEM_BASE", memBase)
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addrMap
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}
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def makeConfigString() = {
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val addrMap = globalAddrMap
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val plicAddr = addrMap("io:int:plic").start
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val prciAddr = addrMap("io:int:prci").start
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val plicInfo = site(PLICKey)
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val xLen = site(XLen)
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val res = new StringBuilder
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res append "plic {\n"
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res append s" priority 0x${plicAddr.toString(16)};\n"
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res append s" pending 0x${(plicAddr + plicInfo.pendingBase).toString(16)};\n"
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res append s" ndevs ${plicInfo.nDevices};\n"
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res append "};\n"
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res append "rtc {\n"
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res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
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res append "};\n"
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if (addrMap contains "mem") {
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res append "ram {\n"
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res append " 0 {\n"
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res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
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res append s" size 0x${addrMap("mem").size.toString(16)};\n"
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res append " };\n"
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res append "};\n"
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}
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res append "core {\n"
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for (i <- 0 until site(NTiles)) { // TODO heterogeneous tiles
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val isa = {
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val m = if (site(MulDivKey).nonEmpty) "m" else ""
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val a = if (site(UseAtomics)) "a" else ""
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val f = if (site(FPUKey).nonEmpty) "f" else ""
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val d = if (site(FPUKey).nonEmpty && site(XLen) > 32) "d" else ""
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val s = if (site(UseVM)) "s" else ""
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s"rv${site(XLen)}i$m$a$f$d$s"
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class BasePlatformConfig extends Config(
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topDefinitions = {
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val configString = new GlobalVariable[String]
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val globalAddrMap = new GlobalVariable[AddrMap]
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val nCoreplexExtClients = new GlobalVariable[Int]
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(pname,site,here) => {
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type PF = PartialFunction[Any,Any]
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def findBy(sname:Any):Any = here[PF](site[Any](sname))(pname)
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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res append s" $i {\n"
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res append " 0 {\n"
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res append s" isa $isa;\n"
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res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
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res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
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res append s" plic {\n"
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res append s" m {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'M')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'M')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'M')).toString(16)};\n"
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res append s" };\n"
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if (site(UseVM)) {
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res append s" s {\n"
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res append s" ie 0x${(plicAddr + plicInfo.enableAddr(i, 'S')).toString(16)};\n"
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res append s" thresh 0x${(plicAddr + plicInfo.threshAddr(i, 'S')).toString(16)};\n"
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res append s" claim 0x${(plicAddr + plicInfo.claimAddr(i, 'S')).toString(16)};\n"
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res append s" };\n"
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}
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res append " };\n"
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res append " };\n"
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res append " };\n"
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case BuildCoreplex =>
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(p: Parameters, c: CoreplexConfig) => Module(new DefaultCoreplex(p, c))
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case NExtTopInterrupts => 2
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// Note that PLIC asserts that this is > 0.
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncMMIOChannels => false
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case ExtMMIOPorts => Nil
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NCoreplexExtClients => nCoreplexExtClients
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => configString
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case GlobalAddrMap => globalAddrMap
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case BuildExampleTop =>
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(p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTop(p))
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case _ => throw new CDEMatchError
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}
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res append "};\n"
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res append (site(ExtraDevices).makeConfigString(addrMap))
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res append '\u0000'
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res.toString.getBytes
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}
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lazy val innerDataBits = 64
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lazy val innerDataBeats = (8 * site(CacheBlockBytes)) / innerDataBits
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pname match {
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//Memory Parameters
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case MIFTagBits => Dump("MIF_TAG_BITS", 5)
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case MIFDataBits => Dump("MIF_DATA_BITS", 64)
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case MIFAddrBits => Dump("MIF_ADDR_BITS",
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site(PAddrBits) - site(CacheBlockOffsetBits))
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case MIFDataBeats => site(CacheBlockBytes) * 8 / site(MIFDataBits)
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case NastiKey => {
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Dump("MEM_STRB_BITS", site(MIFDataBits) / 8)
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NastiParameters(
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dataBits = Dump("MEM_DATA_BITS", site(MIFDataBits)),
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addrBits = Dump("MEM_ADDR_BITS", site(PAddrBits)),
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idBits = Dump("MEM_ID_BITS", site(MIFTagBits)))
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}
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case BuildCoreplex => (p: Parameters) => Module(new DefaultCoreplex(p))
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case NExtTopInterrupts => 2
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case NExtPeripheryInterrupts => site(ExtraDevices).nInterrupts
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// Note that PLIC asserts that this is > 0.
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case NExtInterrupts => site(NExtTopInterrupts) + site(NExtPeripheryInterrupts)
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case AsyncDebugBus => false
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case IncludeJtagDTM => false
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case AsyncMMIOChannels => false
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case ExtraDevices => new EmptyDeviceBlock
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case ExtraTopPorts => (p: Parameters) => new Bundle
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case ExtMMIOPorts => Nil
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case NExtMMIOAXIChannels => 0
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case NExtMMIOAHBChannels => 0
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case NExtMMIOTLChannels => 0
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case ExportMMIOPort => !externalAddrMap.isEmpty
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case AsyncBusChannels => false
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case NExtBusAXIChannels => 0
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case NExternalClients => (if (site(NExtBusAXIChannels) > 0) 1 else 0) +
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site(ExtraDevices).nClientPorts
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case ConnectExtraPorts =>
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(out: Bundle, in: Bundle, p: Parameters) => out <> in
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case HastiId => "Ext"
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case HastiKey("TL") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(TLKey(site(TLId))).dataBits / site(TLKey(site(TLId))).dataBeats)
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case HastiKey("Ext") =>
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HastiParameters(
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addrBits = site(PAddrBits),
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dataBits = site(XLen))
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case AsyncMemChannels => false
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case NMemoryChannels => Dump("N_MEM_CHANNELS", 1)
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case TMemoryChannels => BusType.AXI
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case ExtMemSize => Dump("MEM_SIZE", 0x10000000L)
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case ConfigString => makeConfigString()
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case GlobalAddrMap => globalAddrMap
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case RTCPeriod => 100 // gives 10 MHz RTC assuming 1 GHz uncore clock
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case _ => throw new CDEMatchError
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}})
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})
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class BaseConfig extends Config(new BaseCoreplexConfig ++ new BasePlatformConfig)
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class DefaultConfig extends Config(new WithBlockingL1 ++ new BaseConfig)
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@ -178,7 +89,6 @@ class DefaultBufferlessConfig extends Config(
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class FPGAConfig extends Config (
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(pname,site,here) => pname match {
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case NAcquireTransactors => 4
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case ExportGroundTestStatus => true
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case _ => throw new CDEMatchError
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}
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)
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@ -269,35 +179,12 @@ class TinyConfig extends Config(
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new WithSmallCores ++ new WithRV32 ++
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new WithStatelessBridge ++ new BaseConfig)
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class WithTestRAM extends Config(
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(pname, site, here) => pname match {
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case ExtraDevices => {
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class TestRAMDevice extends DeviceBlock {
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val ramSize = 0x1000
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def nClientPorts = 0
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def addrMapEntries = Seq(
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AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))))
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def builder(
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mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
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clientPorts: Seq[ClientUncachedTileLinkIO],
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interrupts: Seq[Bool],
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extra: Bundle, p: Parameters) {
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val testram = Module(new TileLinkTestRAM(ramSize)(p))
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testram.io <> mmioPorts("testram")
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}
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}
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new TestRAMDevice
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}
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}
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)
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class WithAsyncDebug extends Config (
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(pname, site, here) => pname match {
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case AsyncDebugBus => true
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}
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)
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class WithJtagDTM extends Config (
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(pname, site, here) => pname match {
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case IncludeJtagDTM => true
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@ -1,68 +0,0 @@
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package rocketchip
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import Chisel._
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import junctions._
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import uncore.tilelink._
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import scala.collection.immutable.HashMap
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import cde.{Parameters, Field}
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case object ExtraTopPorts extends Field[Parameters => Bundle]
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case object ExtraDevices extends Field[DeviceBlock]
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abstract class DeviceBlock {
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/** How many client ports will the devices use */
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def nClientPorts: Int
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/** Address map entries for all of the devices */
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def addrMapEntries: Seq[AddrMapEntry]
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/**
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* The total number of interrupt signals coming
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* from all the devices */
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def nInterrupts : Int = 0
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/**
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* The function that elaborates all the extra devices and connects them
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* to the TileLink ports and extra top-level ports.
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*
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* @param mmioPorts A hashmap for the mmio ports.
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* Use the names specified in addrMapEntries to get
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* the mmio port for each device.
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* @param clientPorts All the client ports available for the devices
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* @param interrupts External interrupts from Periphery to Coreplex
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* @param extra The extra top-level IO bundle
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* @param p The CDE parameters for the devices
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*/
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def builder(
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mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
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clientPorts: Seq[ClientUncachedTileLinkIO],
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interrupts : Seq[Bool],
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extra: Bundle, p: Parameters): Unit
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/**
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* Create the config string entry for this device that goes into the
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* Boot ROM. You generally won't need to override this
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*
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* @param fullAddrMap The full global address map
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*/
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def makeConfigString(fullAddrMap: AddrMap): String = {
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addrMapEntries.map { entry =>
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val region = fullAddrMap("io:ext:" + entry.name)
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s"${entry.name} {\n" +
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s" addr 0x${region.start.toString(16)};\n" +
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s" size 0x${region.size.toString(16)}; \n" +
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"}\n"
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}.mkString
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}
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}
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class EmptyDeviceBlock extends DeviceBlock {
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def nClientPorts = 0
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def addrMapEntries = Seq.empty
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def builder(
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mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
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clientPorts: Seq[ClientUncachedTileLinkIO],
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interrupts : Seq[Bool],
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extra: Bundle, p: Parameters) {}
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}
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@ -82,5 +82,5 @@ object RocketChipGenerator extends Generator {
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writeOutputFile(td, s"$longName.prm", ParameterDump.getDump) // Parameters flagged with Dump()
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writeOutputFile(td, s"${names.configs}.knb", world.getKnobs) // Knobs for DSE
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writeOutputFile(td, s"${names.configs}.cst", world.getConstraints) // Constraints for DSE
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writeOutputFile(td, s"${names.configs}.cfg", params(ConfigString).toString) // String for software
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writeOutputFile(td, s"${names.configs}.cfg", params(ConfigString).get) // String for software
|
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}
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@ -37,17 +37,10 @@ case object AsyncMemChannels extends Field[Boolean]
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case object AsyncMMIOChannels extends Field[Boolean]
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/** External address map settings */
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case object ExtMMIOPorts extends Field[Seq[AddrMapEntry]]
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/** Function for building Coreplex */
|
||||
case object BuildCoreplex extends Field[Parameters => Coreplex]
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||||
/** Function for connecting coreplex extra ports to top-level extra ports */
|
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case object ConnectExtraPorts extends Field[(Bundle, Bundle, Parameters) => Unit]
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/** Specifies the size of external memory */
|
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case object ExtMemSize extends Field[Long]
|
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/** Specifies the actual sorce of External Interrupts as Top and Periphery.
|
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* NExtInterrupts = NExtTopInterrupts + NExtPeripheryInterrupts
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**/
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||||
/** Specifies the number of external interrupts */
|
||||
case object NExtTopInterrupts extends Field[Int]
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||||
case object NExtPeripheryInterrupts extends Field[Int]
|
||||
/** Source of RTC. First bundle is TopIO.extra, Second bundle is periphery.io.extra **/
|
||||
case object RTCPeriod extends Field[Int]
|
||||
|
||||
@ -122,29 +115,30 @@ trait PeripheryDebugModule {
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||||
|
||||
/////
|
||||
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||||
trait PeripheryInterrupt extends LazyModule {
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||||
trait PeripheryExtInterrupts extends LazyModule {
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||||
implicit val p: Parameters
|
||||
val pInterrupts: RangeManager
|
||||
|
||||
pInterrupts.add("ext", p(NExtTopInterrupts))
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||||
}
|
||||
|
||||
trait PeripheryInterruptBundle {
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||||
trait PeripheryExtInterruptsBundle {
|
||||
implicit val p: Parameters
|
||||
val interrupts = Vec(p(NExtTopInterrupts), Bool()).asInput
|
||||
}
|
||||
|
||||
trait PeripheryInterruptModule {
|
||||
trait PeripheryExtInterruptsModule {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryInterrupt
|
||||
val io: PeripheryInterruptBundle
|
||||
val outer: PeripheryExtInterrupts
|
||||
val io: PeripheryExtInterruptsBundle
|
||||
val coreplex: Coreplex
|
||||
|
||||
val interrupts_periphery = Vec(p(NExtPeripheryInterrupts), Bool())
|
||||
var interrupts_cnt = 0
|
||||
|
||||
// This places the Periphery Interrupts at Bits [0...]
|
||||
// External interrupts are at the higher Bits.
|
||||
// This may have some implications for prioritization of the interrupts,
|
||||
// but PLIC could do some internal swizzling in the future.
|
||||
coreplex.io.interrupts <> (interrupts_periphery ++ io.interrupts)
|
||||
{
|
||||
val r = outer.pInterrupts.range("ext")
|
||||
((r._1 until r._2) zipWithIndex) foreach { case (c, i) =>
|
||||
coreplex.io.interrupts(c) := io.interrupts(i)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/////
|
||||
@ -169,7 +163,7 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
|
||||
val coreplex: Coreplex
|
||||
|
||||
// Abuse the fact that zip takes the shorter of the two lists
|
||||
((io.mem_axi zip coreplex.io.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
|
||||
((io.mem_axi zip coreplex.io.master.mem) zipWithIndex) foreach { case ((axi, mem), idx) =>
|
||||
val axi_sync = PeripheryUtils.convertTLtoAXI(mem)(outermostParams)
|
||||
axi_sync.ar.bits.cache := UInt("b0011")
|
||||
axi_sync.aw.bits.cache := UInt("b0011")
|
||||
@ -179,11 +173,11 @@ trait PeripheryMasterMemModule extends HasPeripheryParameters {
|
||||
)
|
||||
}
|
||||
|
||||
(io.mem_ahb zip coreplex.io.mem) foreach { case (ahb, mem) =>
|
||||
(io.mem_ahb zip coreplex.io.master.mem) foreach { case (ahb, mem) =>
|
||||
ahb <> PeripheryUtils.convertTLtoAHB(mem, atomics = false)(outermostParams)
|
||||
}
|
||||
|
||||
(io.mem_tl zip coreplex.io.mem) foreach { case (tl, mem) =>
|
||||
(io.mem_tl zip coreplex.io.master.mem) foreach { case (tl, mem) =>
|
||||
tl <> ClientUncachedTileLinkEnqueuer(mem, 2)(outermostParams)
|
||||
}
|
||||
}
|
||||
@ -245,6 +239,9 @@ trait PeripheryMasterMMIOModule extends HasPeripheryParameters {
|
||||
|
||||
trait PeripherySlave extends LazyModule {
|
||||
implicit val p: Parameters
|
||||
val pBusMasters: RangeManager
|
||||
|
||||
if (p(NExtBusAXIChannels) > 0) pBusMasters.add("ext", 1) // NExtBusAXIChannels are arbitrated into one TL port
|
||||
}
|
||||
|
||||
trait PeripherySlaveBundle extends HasPeripheryParameters {
|
||||
@ -270,7 +267,65 @@ trait PeripherySlaveModule extends HasPeripheryParameters {
|
||||
}
|
||||
val conv = Module(new TileLinkIONastiIOConverter()(innerParams))
|
||||
conv.io.nasti <> arb.io.slave
|
||||
coreplex.io.ext_clients.head <> conv.io.tl
|
||||
require(p(NExternalClients) == 1, "external devices can't slave ports. wait for tilelink2!")
|
||||
|
||||
val r = outer.pBusMasters.range("ext")
|
||||
require(r._2 - r._1 == 1, "RangeManager should return 1 slot")
|
||||
coreplex.io.slave(r._1) <> conv.io.tl
|
||||
}
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait PeripheryTestRAM extends LazyModule {
|
||||
implicit val p: Parameters
|
||||
val pDevices: ResourceManager[AddrMapEntry]
|
||||
|
||||
val ramSize = 0x1000
|
||||
pDevices.add(AddrMapEntry("testram", MemSize(ramSize, MemAttr(AddrMapProt.RW))))
|
||||
}
|
||||
|
||||
trait PeripheryTestRAMBundle {
|
||||
implicit val p: Parameters
|
||||
}
|
||||
|
||||
trait PeripheryTestRAMModule extends HasPeripheryParameters {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryTestRAM
|
||||
val io: PeripheryTestRAMBundle
|
||||
val mmioNetwork: Option[TileLinkRecursiveInterconnect]
|
||||
|
||||
val testram = Module(new TileLinkTestRAM(outer.ramSize)(innerMMIOParams))
|
||||
testram.io <> mmioNetwork.get.port("testram")
|
||||
}
|
||||
|
||||
/////
|
||||
|
||||
trait PeripheryTestBusMaster extends LazyModule {
|
||||
implicit val p: Parameters
|
||||
val pBusMasters: RangeManager
|
||||
val pDevices: ResourceManager[AddrMapEntry]
|
||||
|
||||
pBusMasters.add("busmaster", 1)
|
||||
pDevices.add(AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW))))
|
||||
}
|
||||
|
||||
trait PeripheryTestBusMasterBundle {
|
||||
implicit val p: Parameters
|
||||
}
|
||||
|
||||
trait PeripheryTestBusMasterModule {
|
||||
implicit val p: Parameters
|
||||
val outer: PeripheryTestBusMaster
|
||||
val io: PeripheryTestBusMasterBundle
|
||||
val mmioNetwork: Option[TileLinkRecursiveInterconnect]
|
||||
val coreplex: Coreplex
|
||||
|
||||
val busmaster = Module(new groundtest.ExampleBusMaster()(p))
|
||||
busmaster.io.mmio <> mmioNetwork.get.port("busmaster")
|
||||
|
||||
{
|
||||
val r = outer.pBusMasters.range("busmaster")
|
||||
require(r._2 - r._1 == 1, "RangeManager should return 1 slot")
|
||||
coreplex.io.slave(r._1) <> busmaster.io.mem
|
||||
}
|
||||
}
|
||||
|
||||
@ -26,7 +26,7 @@ class WithUnitTest extends Config(
|
||||
DefaultTestSuites.groundtest32
|
||||
TestGeneration.addSuite(groundtest("p"))
|
||||
TestGeneration.addSuite(DefaultTestSuites.emptyBmarks)
|
||||
(p: Parameters) => Module(new UnitTestCoreplex(p))
|
||||
(p: Parameters, c: CoreplexConfig) => Module(new UnitTestCoreplex(p, c))
|
||||
}
|
||||
case UnitTests => (testParams: Parameters) =>
|
||||
JunctionsUnitTests(testParams) ++ UncoreUnitTests(testParams)
|
||||
@ -42,7 +42,8 @@ class UnitTestConfig extends Config(new WithUnitTest ++ new BaseConfig)
|
||||
|
||||
class WithGroundTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case BuildCoreplex => (p: Parameters) => Module(new GroundTestCoreplex(p))
|
||||
case BuildCoreplex =>
|
||||
(p: Parameters, c: CoreplexConfig) => Module(new GroundTestCoreplex(p, c))
|
||||
case TLKey("L1toL2") => {
|
||||
val useMEI = site(NTiles) <= 1 && site(NCachedTileLinkPorts) <= 1
|
||||
TileLinkParameters(
|
||||
@ -51,7 +52,7 @@ class WithGroundTest extends Config(
|
||||
else new MESICoherence(site(L2DirectoryRepresentation))),
|
||||
nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1,
|
||||
nCachingClients = site(NCachedTileLinkPorts),
|
||||
nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts),
|
||||
nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
|
||||
maxClientXacts = ((site(DCacheKey).nMSHRs + 1) +:
|
||||
site(GroundTestKey).map(_.maxXacts))
|
||||
.reduce(max(_, _)),
|
||||
@ -79,6 +80,8 @@ class WithGroundTest extends Config(
|
||||
}
|
||||
}
|
||||
}
|
||||
case BuildExampleTop =>
|
||||
(p: Parameters) => uncore.tilelink2.LazyModule(new ExampleTopWithTestRAM(p))
|
||||
case FPUKey => None
|
||||
case UseAtomics => false
|
||||
case UseCompressed => false
|
||||
@ -89,7 +92,7 @@ class WithGroundTest extends Config(
|
||||
class GroundTestConfig extends Config(new WithGroundTest ++ new BaseConfig)
|
||||
|
||||
class ComparatorConfig extends Config(
|
||||
new WithTestRAM ++ new WithComparator ++ new GroundTestConfig)
|
||||
new WithComparator ++ new GroundTestConfig)
|
||||
class ComparatorL2Config extends Config(
|
||||
new WithAtomics ++ new WithPrefetches ++
|
||||
new WithL2Cache ++ new ComparatorConfig)
|
||||
@ -147,60 +150,3 @@ class MIF32BitMemtestConfig extends Config(
|
||||
|
||||
class PCIeMockupTestConfig extends Config(
|
||||
new WithPCIeMockupTest ++ new GroundTestConfig)
|
||||
|
||||
class WithDirectGroundTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case ExportGroundTestStatus => true
|
||||
case BuildCoreplex => (p: Parameters) => Module(new DirectGroundTestCoreplex(p))
|
||||
case ExtraCoreplexPorts => (p: Parameters) =>
|
||||
if (p(ExportGroundTestStatus)) new GroundTestStatus else new Bundle
|
||||
case ExtraTopPorts => (p: Parameters) =>
|
||||
if (p(ExportGroundTestStatus)) new GroundTestStatus else new Bundle
|
||||
case TLKey("Outermost") => site(TLKey("L2toMC")).copy(
|
||||
maxClientXacts = site(GroundTestKey)(0).maxXacts,
|
||||
maxClientsPerPort = site(NBanksPerMemoryChannel),
|
||||
dataBeats = site(MIFDataBeats))
|
||||
case NBanksPerMemoryChannel => site(GroundTestKey)(0).uncached
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class DirectGroundTestConfig extends Config(
|
||||
new WithDirectGroundTest ++ new GroundTestConfig)
|
||||
class DirectMemtestConfig extends Config(
|
||||
new WithDirectMemtest ++ new DirectGroundTestConfig)
|
||||
class DirectComparatorConfig extends Config(
|
||||
new WithDirectComparator ++ new DirectGroundTestConfig)
|
||||
|
||||
class DirectMemtestFPGAConfig extends Config(
|
||||
new FPGAConfig ++ new DirectMemtestConfig)
|
||||
class DirectComparatorFPGAConfig extends Config(
|
||||
new FPGAConfig ++ new DirectComparatorConfig)
|
||||
|
||||
class WithBusMasterTest extends Config(
|
||||
(pname, site, here) => pname match {
|
||||
case GroundTestKey => Seq.fill(site(NTiles)) {
|
||||
GroundTestTileSettings(uncached = 1)
|
||||
}
|
||||
case BuildGroundTest =>
|
||||
(p: Parameters) => Module(new BusMasterTest()(p))
|
||||
case ExtraDevices => {
|
||||
class BusMasterDevice extends DeviceBlock {
|
||||
def nClientPorts = 1
|
||||
def addrMapEntries = Seq(
|
||||
AddrMapEntry("busmaster", MemSize(4096, MemAttr(AddrMapProt.RW))))
|
||||
def builder(
|
||||
mmioPorts: HashMap[String, ClientUncachedTileLinkIO],
|
||||
clientPorts: Seq[ClientUncachedTileLinkIO],
|
||||
interrupts : Seq[Bool],
|
||||
extra: Bundle, p: Parameters) {
|
||||
val busmaster = Module(new ExampleBusMaster()(p))
|
||||
busmaster.io.mmio <> mmioPorts("busmaster")
|
||||
clientPorts.head <> busmaster.io.mem
|
||||
}
|
||||
}
|
||||
new BusMasterDevice
|
||||
}
|
||||
case _ => throw new CDEMatchError
|
||||
})
|
||||
|
||||
class BusMasterTestConfig extends Config(new WithBusMasterTest ++ new GroundTestConfig)
|
||||
|
||||
@ -7,11 +7,13 @@ import cde.{Parameters, Field}
|
||||
import rocket.Util._
|
||||
import junctions._
|
||||
|
||||
class TestHarness(implicit p: Parameters) extends Module {
|
||||
case object BuildExampleTop extends Field[Parameters => ExampleTop]
|
||||
|
||||
class TestHarness(implicit val p: Parameters) extends Module with HasAddrMapParameters {
|
||||
val io = new Bundle {
|
||||
val success = Bool(OUTPUT)
|
||||
}
|
||||
val dut = uncore.tilelink2.LazyModule(new ExampleTop(p)).module
|
||||
val dut = p(BuildExampleTop)(p).module
|
||||
|
||||
// This test harness isn't especially flexible yet
|
||||
require(dut.io.mem_clk.isEmpty)
|
||||
@ -29,7 +31,7 @@ class TestHarness(implicit p: Parameters) extends Module {
|
||||
int := false
|
||||
|
||||
if (dut.io.mem_axi.nonEmpty) {
|
||||
val memSize = p(GlobalAddrMap)("mem").size
|
||||
val memSize = addrMap("mem").size
|
||||
require(memSize % dut.io.mem_axi.size == 0)
|
||||
for (axi <- dut.io.mem_axi)
|
||||
Module(new SimAXIMem(memSize / dut.io.mem_axi.size)).io.axi <> axi
|
||||
|
||||
@ -3,49 +3,93 @@
|
||||
package rocketchip
|
||||
|
||||
import Chisel._
|
||||
import cde.{Parameters}
|
||||
import cde.{Parameters, Field}
|
||||
import junctions._
|
||||
import uncore.tilelink._
|
||||
import uncore.tilelink2.{LazyModule, LazyModuleImp}
|
||||
import uncore.devices._
|
||||
import rocket._
|
||||
import rocket.Util._
|
||||
import coreplex._
|
||||
|
||||
// the following parameters will be refactored properly with TL2
|
||||
case object GlobalAddrMap extends Field[GlobalVariable[AddrMap]]
|
||||
case object ConfigString extends Field[GlobalVariable[String]]
|
||||
case object NCoreplexExtClients extends Field[GlobalVariable[Int]]
|
||||
|
||||
/** Base Top with no Periphery */
|
||||
|
||||
abstract class BaseTop(val p: Parameters) extends LazyModule
|
||||
abstract class BaseTop(val p: Parameters) extends LazyModule {
|
||||
// the following variables will be refactored properly with TL2
|
||||
val pInterrupts = new RangeManager
|
||||
val pBusMasters = new RangeManager
|
||||
val pDevices = new ResourceManager[AddrMapEntry]
|
||||
}
|
||||
|
||||
class BaseTopBundle(val p: Parameters, val c: Coreplex) extends ParameterizedBundle()(p) {
|
||||
val success = c.hasSuccessFlag.option(Bool(OUTPUT))
|
||||
}
|
||||
|
||||
class BaseTopModule[L <: BaseTop, B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
|
||||
val coreplex = p(BuildCoreplex)(p)
|
||||
class BaseTopModule[+L <: BaseTop, +B <: BaseTopBundle](val p: Parameters, l: L, b: Coreplex => B) extends LazyModuleImp(l) {
|
||||
val outer: L = l
|
||||
|
||||
val c = CoreplexConfig(
|
||||
nTiles = p(NTiles),
|
||||
nExtInterrupts = outer.pInterrupts.sum,
|
||||
nSlaves = outer.pBusMasters.sum,
|
||||
hasSupervisor = p(UseVM),
|
||||
hasExtMMIOPort = !(outer.pDevices.get.isEmpty && p(ExtMMIOPorts).isEmpty)
|
||||
)
|
||||
|
||||
p(NCoreplexExtClients).assign(outer.pBusMasters.sum)
|
||||
p(GlobalAddrMap).assign(GenerateGlobalAddrMap(p, outer.pDevices.get))
|
||||
p(ConfigString).assign(GenerateConfigString(p, c, outer.pDevices.get))
|
||||
|
||||
println("Generated Address Map")
|
||||
for (entry <- p(GlobalAddrMap).get.flatten) {
|
||||
val name = entry.name
|
||||
val start = entry.region.start
|
||||
val end = entry.region.start + entry.region.size - 1
|
||||
println(f"\t$name%s $start%x - $end%x")
|
||||
}
|
||||
|
||||
println("Generated Configuration String")
|
||||
println(p(ConfigString).get)
|
||||
|
||||
val coreplex = p(BuildCoreplex)(p, c)
|
||||
val io: B = b(coreplex)
|
||||
|
||||
io.success zip coreplex.io.success map { case (x, y) => x := y }
|
||||
coreplex.io.rtcTick := Counter(p(RTCPeriod)).inc()
|
||||
|
||||
val mmioNetwork = p(ExportMMIOPort).option(
|
||||
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).subMap("io:ext"))(
|
||||
val mmioNetwork = c.hasExtMMIOPort.option(
|
||||
Module(new TileLinkRecursiveInterconnect(1, p(GlobalAddrMap).get.subMap("io:ext"))(
|
||||
p.alterPartial({ case TLId => "L2toMMIO" }))))
|
||||
mmioNetwork.foreach { _.io.in.head <> coreplex.io.mmio.get }
|
||||
mmioNetwork.foreach { _.io.in.head <> coreplex.io.master.mmio.get }
|
||||
}
|
||||
|
||||
|
||||
/** Example Top with Periphery */
|
||||
|
||||
class ExampleTop(p: Parameters) extends BaseTop(p)
|
||||
with PeripheryDebug with PeripheryInterrupt
|
||||
with PeripheryDebug with PeripheryExtInterrupts
|
||||
with PeripheryMasterMem with PeripheryMasterMMIO with PeripherySlave {
|
||||
lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
|
||||
override lazy val module = Module(new ExampleTopModule(p, this, new ExampleTopBundle(p, _)))
|
||||
}
|
||||
|
||||
class ExampleTopBundle(p: Parameters, c: Coreplex) extends BaseTopBundle(p, c)
|
||||
with PeripheryDebugBundle with PeripheryInterruptBundle
|
||||
with PeripheryDebugBundle with PeripheryExtInterruptsBundle
|
||||
with PeripheryMasterMemBundle with PeripheryMasterMMIOBundle with PeripherySlaveBundle
|
||||
|
||||
class ExampleTopModule[L <: ExampleTop, B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
|
||||
with PeripheryDebugModule with PeripheryInterruptModule
|
||||
class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: Coreplex => B) extends BaseTopModule(p, l, b)
|
||||
with PeripheryDebugModule with PeripheryExtInterruptsModule
|
||||
with PeripheryMasterMemModule with PeripheryMasterMMIOModule with PeripherySlaveModule
|
||||
|
||||
/** Example Top with TestRAM */
|
||||
class ExampleTopWithTestRAM(p: Parameters) extends ExampleTop(p)
|
||||
with PeripheryTestRAM {
|
||||
override lazy val module = Module(new ExampleTopWithTestRAMModule(p, this, new ExampleTopWithTestRAMBundle(p, _)))
|
||||
}
|
||||
|
||||
class ExampleTopWithTestRAMBundle(p: Parameters, c: Coreplex) extends ExampleTopBundle(p, c)
|
||||
with PeripheryTestRAMBundle
|
||||
|
||||
class ExampleTopWithTestRAMModule[+L <: ExampleTopWithTestRAM, +B <: ExampleTopWithTestRAMBundle](p: Parameters, l: L, b: Coreplex => B) extends ExampleTopModule(p, l, b)
|
||||
with PeripheryTestRAMModule
|
||||
|
||||
149
src/main/scala/rocketchip/Utils.scala
Normal file
149
src/main/scala/rocketchip/Utils.scala
Normal file
@ -0,0 +1,149 @@
|
||||
// See LICENSE for license details.
|
||||
|
||||
package rocketchip
|
||||
|
||||
import cde.{Parameters, Dump}
|
||||
import junctions._
|
||||
import uncore.devices._
|
||||
import rocket._
|
||||
import rocket.Util._
|
||||
import coreplex._
|
||||
|
||||
class RangeManager {
|
||||
private var finalized = false
|
||||
private val l = collection.mutable.HashMap[String, Int]()
|
||||
def add(name: String, element: Int) = { require(!finalized); l += (name -> element) }
|
||||
def rangeMap = {
|
||||
finalized = true
|
||||
l map {
|
||||
var sum = 0
|
||||
x => { sum += x._2; (x._1 -> (sum-x._2, sum)) }
|
||||
}
|
||||
}
|
||||
def range(name: String) = rangeMap(name)
|
||||
def print = {
|
||||
rangeMap map { case (name, (start, end)) =>
|
||||
println(s"${name} on port ${start}-${end-1}")
|
||||
}
|
||||
}
|
||||
def sum = {
|
||||
finalized = true
|
||||
l.map(_._2).sum
|
||||
}
|
||||
}
|
||||
|
||||
class ResourceManager[T] {
|
||||
private var finalized = false
|
||||
private val l = collection.mutable.ArrayBuffer[T]()
|
||||
def add(element: T) = { require(!finalized); l += element }
|
||||
def add(list: Seq[T]) = { require(!finalized); l ++= list }
|
||||
def get: Seq[T] = { finalized = true; l }
|
||||
}
|
||||
|
||||
class GlobalVariable[T] {
|
||||
private var assigned = false
|
||||
private var variable: T = _
|
||||
def assign(value: T) = { require(!assigned); assigned = true; variable = value }
|
||||
def get: T = { require(assigned); variable }
|
||||
}
|
||||
|
||||
object GenerateGlobalAddrMap {
|
||||
def apply(p: Parameters, pDevicesEntries: Seq[AddrMapEntry]) = {
|
||||
lazy val intIOAddrMap: AddrMap = {
|
||||
val entries = collection.mutable.ArrayBuffer[AddrMapEntry]()
|
||||
entries += AddrMapEntry("debug", MemSize(4096, MemAttr(AddrMapProt.RWX)))
|
||||
entries += AddrMapEntry("bootrom", MemSize(4096, MemAttr(AddrMapProt.RX)))
|
||||
entries += AddrMapEntry("plic", MemRange(0x40000000, 0x4000000, MemAttr(AddrMapProt.RW)))
|
||||
entries += AddrMapEntry("prci", MemSize(0x4000000, MemAttr(AddrMapProt.RW)))
|
||||
if (p(DataScratchpadSize) > 0) { // TODO heterogeneous tiles
|
||||
require(p(NTiles) == 1) // TODO relax this
|
||||
require(p(NMemoryChannels) == 0) // TODO allow both scratchpad & DRAM
|
||||
entries += AddrMapEntry("dmem0", MemRange(0x80000000L, BigInt(p(DataScratchpadSize)), MemAttr(AddrMapProt.RWX)))
|
||||
}
|
||||
new AddrMap(entries)
|
||||
}
|
||||
|
||||
lazy val extIOAddrMap = new AddrMap(
|
||||
pDevicesEntries ++ p(ExtMMIOPorts),
|
||||
start = BigInt("50000000", 16),
|
||||
collapse = true)
|
||||
|
||||
val memBase = 0x80000000L
|
||||
val memSize = p(ExtMemSize)
|
||||
Dump("MEM_BASE", memBase)
|
||||
|
||||
val intern = AddrMapEntry("int", intIOAddrMap)
|
||||
val extern = AddrMapEntry("ext", extIOAddrMap)
|
||||
val io = AddrMapEntry("io", AddrMap((intern +: (!extIOAddrMap.isEmpty).option(extern).toSeq):_*))
|
||||
val mem = AddrMapEntry("mem", MemRange(memBase, memSize, MemAttr(AddrMapProt.RWX, true)))
|
||||
AddrMap((io +: (p(NMemoryChannels) > 0).option(mem).toSeq):_*)
|
||||
}
|
||||
}
|
||||
|
||||
object GenerateConfigString {
|
||||
def apply(p: Parameters, c: CoreplexConfig, pDevicesEntries: Seq[AddrMapEntry]) = {
|
||||
val addrMap = p(GlobalAddrMap).get
|
||||
val plicAddr = addrMap("io:int:plic").start
|
||||
val prciAddr = addrMap("io:int:prci").start
|
||||
val xLen = p(XLen)
|
||||
val res = new StringBuilder
|
||||
res append "plic {\n"
|
||||
res append s" priority 0x${plicAddr.toString(16)};\n"
|
||||
res append s" pending 0x${(plicAddr + c.plicKey.pendingBase).toString(16)};\n"
|
||||
res append s" ndevs ${c.plicKey.nDevices};\n"
|
||||
res append "};\n"
|
||||
res append "rtc {\n"
|
||||
res append s" addr 0x${(prciAddr + PRCI.time).toString(16)};\n"
|
||||
res append "};\n"
|
||||
if (addrMap contains "mem") {
|
||||
res append "ram {\n"
|
||||
res append " 0 {\n"
|
||||
res append s" addr 0x${addrMap("mem").start.toString(16)};\n"
|
||||
res append s" size 0x${addrMap("mem").size.toString(16)};\n"
|
||||
res append " };\n"
|
||||
res append "};\n"
|
||||
}
|
||||
res append "core {\n"
|
||||
for (i <- 0 until c.nTiles) { // TODO heterogeneous tiles
|
||||
val isa = {
|
||||
val m = if (p(MulDivKey).nonEmpty) "m" else ""
|
||||
val a = if (p(UseAtomics)) "a" else ""
|
||||
val f = if (p(FPUKey).nonEmpty) "f" else ""
|
||||
val d = if (p(FPUKey).nonEmpty && p(XLen) > 32) "d" else ""
|
||||
val s = if (c.hasSupervisor) "s" else ""
|
||||
s"rv${p(XLen)}i$m$a$f$d$s"
|
||||
}
|
||||
res append s" $i {\n"
|
||||
res append " 0 {\n"
|
||||
res append s" isa $isa;\n"
|
||||
res append s" timecmp 0x${(prciAddr + PRCI.timecmp(i)).toString(16)};\n"
|
||||
res append s" ipi 0x${(prciAddr + PRCI.msip(i)).toString(16)};\n"
|
||||
res append s" plic {\n"
|
||||
res append s" m {\n"
|
||||
res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'M')).toString(16)};\n"
|
||||
res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'M')).toString(16)};\n"
|
||||
res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'M')).toString(16)};\n"
|
||||
res append s" };\n"
|
||||
if (c.hasSupervisor) {
|
||||
res append s" s {\n"
|
||||
res append s" ie 0x${(plicAddr + c.plicKey.enableAddr(i, 'S')).toString(16)};\n"
|
||||
res append s" thresh 0x${(plicAddr + c.plicKey.threshAddr(i, 'S')).toString(16)};\n"
|
||||
res append s" claim 0x${(plicAddr + c.plicKey.claimAddr(i, 'S')).toString(16)};\n"
|
||||
res append s" };\n"
|
||||
}
|
||||
res append " };\n"
|
||||
res append " };\n"
|
||||
res append " };\n"
|
||||
}
|
||||
res append "};\n"
|
||||
pDevicesEntries foreach { entry =>
|
||||
val region = addrMap("io:ext:" + entry.name)
|
||||
res append s"${entry.name} {\n"
|
||||
res append s" addr 0x${region.start.toString(16)};\n"
|
||||
res append s" size 0x${region.size.toString(16)}; \n"
|
||||
res append "}\n"
|
||||
}
|
||||
res append '\u0000'
|
||||
res.toString
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user