now able to add periphery devices through traits

Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits.
This commit gets rid of the "extra" infrastructure to add periphery devices into Top.

src/main/scala/groundtest/TraceGen.scala

@@ -176,6 +176,7 @@ class TagMan(val logNumTags : Int) extends Module {
 
 class TraceGenerator(id: Int)
     (implicit p: Parameters) extends L1HellaCacheModule()(p)
+                                with HasAddrMapParameters
                                 with HasTraceGenParams {
   val io = new Bundle {
     val finished = Bool(OUTPUT)
@@ -197,8 +198,7 @@ class TraceGenerator(id: Int)
   // Address bag, shared by all cores, taken from module parameters.
   // In addition, there is a per-core random selection of extra addresses.
 
-  val addrHashMap = p(GlobalAddrMap)
-  val baseAddr = addrHashMap("mem").start + 0x01000000
+  val baseAddr = addrMap("mem").start + 0x01000000
 
   val bagOfAddrs = addressBag.map(x => UInt(x, numBitsInWord))