now able to add periphery devices through traits
Unfortunately, I had to touch a lot of code, which weren't quite possible to split up into multiple commits. This commit gets rid of the "extra" infrastructure to add periphery devices into Top.
This commit is contained in:
Yunsup Lee
@ -11,6 +11,7 @@ import uncore.devices._
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import uncore.converters._
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import rocket._
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import rocket.Util._
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import rocketchip.{GlobalAddrMap, NCoreplexExtClients}
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import scala.math.max
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import scala.collection.mutable.{LinkedHashSet, ListBuffer}
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import DefaultTestSuites._
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@ -127,7 +128,6 @@ class BaseCoreplexConfig extends Config (
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case MulDivKey => Some(MulDivConfig(mulUnroll = 8, mulEarlyOut = true, divEarlyOut = true))
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case UseAtomics => true
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case UseCompressed => true
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case PLICKey => PLICConfig(site(NTiles), site(UseVM), site(NExtInterrupts), 0)
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case DMKey => new DefaultDebugModuleConfig(site(NTiles), site(XLen))
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case NCustomMRWCSRs => 0
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case ResetVector => BigInt(0x1000)
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@ -145,7 +145,7 @@ class BaseCoreplexConfig extends Config (
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else new MESICoherence(site(L2DirectoryRepresentation))),
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nManagers = site(NBanksPerMemoryChannel)*site(NMemoryChannels) + 1 /* MMIO */,
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nCachingClients = site(NCachedTileLinkPorts),
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nCachelessClients = site(NExternalClients) + site(NUncachedTileLinkPorts),
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nCachelessClients = site(NCoreplexExtClients).get + site(NUncachedTileLinkPorts),
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maxClientXacts = max_int(
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// L1 cache
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site(DCacheKey).nMSHRs + 1 /* IOMSHR */,
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@ -176,7 +176,7 @@ class BaseCoreplexConfig extends Config (
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TileLinkParameters(
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coherencePolicy = new MICoherence(
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new NullRepresentation(site(NBanksPerMemoryChannel))),
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nManagers = site(GlobalAddrMap).subMap("io").numSlaves,
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nManagers = site(GlobalAddrMap).get.subMap("io").numSlaves,
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nCachingClients = 0,
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nCachelessClients = 1,
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maxClientXacts = 4,
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@ -194,7 +194,6 @@ class BaseCoreplexConfig extends Config (
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case CacheBlockBytes => Dump("CACHE_BLOCK_BYTES", 64)
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case CacheBlockOffsetBits => log2Up(here(CacheBlockBytes))
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case EnableL2Logging => false
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case ExtraCoreplexPorts => (p: Parameters) => new Bundle
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case RegressionTestNames => LinkedHashSet(
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"rv64ud-v-fcvt",
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"rv64ud-p-fdiv",
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@ -14,6 +14,8 @@ import rocket.Util._
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import java.nio.{ByteBuffer,ByteOrder}
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import java.nio.file.{Files, Paths}
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/** Function for building Coreplex */
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case object BuildCoreplex extends Field[(Parameters, CoreplexConfig) => Coreplex]
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/** Number of memory channels */
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case object NMemoryChannels extends Field[Int]
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/** Number of banks per memory channel */
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@ -24,24 +26,11 @@ case object BankIdLSB extends Field[Int]
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case object BuildL2CoherenceManager extends Field[(Int, Parameters) => CoherenceAgent]
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/** Function for building some kind of tile connected to a reset signal */
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case object BuildTiles extends Field[Seq[(Bool, Parameters) => Tile]]
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/** A string describing on-chip devices, readable by target software */
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case object ConfigString extends Field[Array[Byte]]
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/** Number of external interrupt sources */
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case object NExtInterrupts extends Field[Int]
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/** Interrupt controller configuration */
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case object PLICKey extends Field[PLICConfig]
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/** The file to read the BootROM contents from */
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case object BootROMFile extends Field[String]
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/** Export an external MMIO slave port */
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case object ExportMMIOPort extends Field[Boolean]
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/** Expose additional TileLink client ports */
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case object NExternalClients extends Field[Int]
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/** Extra top-level ports exported from the coreplex */
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case object ExtraCoreplexPorts extends Field[Parameters => Bundle]
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trait HasCoreplexParameters {
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implicit val p: Parameters
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lazy val nTiles = p(NTiles)
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lazy val nMemChannels = p(NMemoryChannels)
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lazy val nBanksPerMemChannel = p(NBanksPerMemoryChannel)
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lazy val nBanks = nMemChannels*nBanksPerMemChannel
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@ -49,20 +38,31 @@ trait HasCoreplexParameters {
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lazy val innerParams = p.alterPartial({ case TLId => "L1toL2" })
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lazy val outermostParams = p.alterPartial({ case TLId => "Outermost" })
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lazy val outermostMMIOParams = p.alterPartial({ case TLId => "MMIO_Outermost" })
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lazy val nExtClients = p(NExternalClients)
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lazy val exportMMIO = p(ExportMMIOPort)
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lazy val configString = p(rocketchip.ConfigString).get
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lazy val globalAddrMap = p(rocketchip.GlobalAddrMap).get
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}
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abstract class Coreplex(implicit val p: Parameters) extends Module
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case class CoreplexConfig(
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nTiles: Int,
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nExtInterrupts: Int,
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nSlaves: Int,
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hasSupervisor: Boolean,
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hasExtMMIOPort: Boolean)
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{
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val plicKey = PLICConfig(nTiles, hasSupervisor, nExtInterrupts, 0)
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}
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abstract class Coreplex(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Module
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with HasCoreplexParameters {
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class CoreplexIO(implicit val p: Parameters) extends Bundle {
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val ext_clients = Vec(nExtClients, new ClientUncachedTileLinkIO()(innerParams)).flip
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val mmio = p(ExportMMIOPort).option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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val interrupts = Vec(p(NExtInterrupts), Bool()).asInput
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class CoreplexIO(implicit val p: Parameters, implicit val c: CoreplexConfig) extends Bundle {
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val master = new Bundle {
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val mem = Vec(nMemChannels, new ClientUncachedTileLinkIO()(outermostParams))
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val mmio = c.hasExtMMIOPort.option(new ClientUncachedTileLinkIO()(outermostMMIOParams))
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}
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val slave = Vec(c.nSlaves, new ClientUncachedTileLinkIO()(innerParams)).flip
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val interrupts = Vec(c.nExtInterrupts, Bool()).asInput
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val debug = new DebugBusIO()(p).flip
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val rtcTick = Bool(INPUT)
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val extra = p(ExtraCoreplexPorts)(p)
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val success: Option[Bool] = hasSuccessFlag.option(Bool(OUTPUT))
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}
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@ -70,16 +70,16 @@ abstract class Coreplex(implicit val p: Parameters) extends Module
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val io = new CoreplexIO
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}
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class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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class DefaultCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
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// Build a set of Tiles
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val tileResets = Wire(Vec(nTiles, Bool()))
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val tileResets = Wire(Vec(tc.nTiles, Bool()))
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val tileList = p(BuildTiles).zip(tileResets).map {
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case (tile, rst) => tile(rst, p)
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}
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val nCachedPorts = tileList.map(tile => tile.io.cached.size).reduce(_ + _)
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val nUncachedPorts = tileList.map(tile => tile.io.uncached.size).reduce(_ + _)
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printConfigString
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// Build an uncore backing the Tiles
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buildUncore(p.alterPartial({
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case HastiId => "TL"
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case TLId => "L1toL2"
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@ -87,25 +87,13 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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case NUncachedTileLinkPorts => nUncachedPorts
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}))
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def printConfigString(implicit p: Parameters) = {
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println("Generated Address Map")
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for (entry <- p(GlobalAddrMap).flatten) {
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val name = entry.name
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val start = entry.region.start
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val end = entry.region.start + entry.region.size - 1
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println(f"\t$name%s $start%x - $end%x")
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}
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println("Generated Configuration String")
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println(new String(p(ConfigString)))
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}
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def buildUncore(implicit p: Parameters) = {
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// Create a simple L1toL2 NoC between the tiles and the banks of outer memory
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// Cached ports are first in client list, making sharerToClientId just an indentity function
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// addrToBank is sed to hash physical addresses (of cache blocks) to banks (and thereby memory channels)
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def sharerToClientId(sharerId: UInt) = sharerId
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def addrToBank(addr: UInt): UInt = if (nBanks == 0) UInt(0) else {
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val isMemory = p(GlobalAddrMap).isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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val isMemory = globalAddrMap.isInRegion("mem", addr << log2Up(p(CacheBlockBytes)))
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Mux(isMemory, addr.extract(lsb + log2Ceil(nBanks) - 1, lsb), UInt(nBanks))
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}
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val preBuffering = TileLinkDepths(1,1,2,2,0)
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@ -124,7 +112,7 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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// Wire the tiles to the TileLink client ports of the L1toL2 network,
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// and coherence manager(s) to the other side
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l1tol2net.io.clients_cached <> tileList.map(_.io.cached).flatten
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l1tol2net.io.clients_uncached <> tileList.map(_.io.uncached).flatten ++ io.ext_clients
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l1tol2net.io.clients_uncached <> tileList.map(_.io.uncached).flatten ++ io.slave
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l1tol2net.io.managers <> managerEndpoints.map(_.innerTL) :+ mmioManager.io.inner
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// Create a converter between TileLinkIO and MemIO for each channel
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@ -138,7 +126,7 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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TileLinkWidthAdapter(icPort, unwrap.io.out)
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}
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io.mem <> mem_ic.io.out
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io.master.mem <> mem_ic.io.out
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buildMMIONetwork(ClientUncachedTileLinkEnqueuer(mmioManager.io.outer, 1))(
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p.alterPartial({case TLId => "L2toMMIO"}))
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@ -151,7 +139,10 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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rom.order(ByteOrder.LITTLE_ENDIAN)
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// for now, have the reset vector jump straight to memory
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val memBase = (if (p(GlobalAddrMap) contains "mem") p(GlobalAddrMap)("mem") else p(GlobalAddrMap)("io:int:dmem0")).start
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val memBase = (
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if (globalAddrMap contains "mem") globalAddrMap("mem")
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else globalAddrMap("io:int:dmem0")
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).start
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val resetToMemDist = memBase - p(ResetVector)
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require(resetToMemDist == (resetToMemDist.toInt >> 12 << 12))
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val configStringAddr = p(ResetVector).toInt + rom.capacity
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@ -159,17 +150,17 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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require(rom.getInt(12) == 0,
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"Config string address position should not be occupied by code")
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rom.putInt(12, configStringAddr)
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rom.array() ++ p(ConfigString).toSeq
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rom.array() ++ (configString.getBytes.toSeq)
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}
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def buildMMIONetwork(mmio: ClientUncachedTileLinkIO)(implicit p: Parameters) = {
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val ioAddrMap = p(GlobalAddrMap).subMap("io")
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val ioAddrMap = globalAddrMap.subMap("io")
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val mmioNetwork = Module(new TileLinkRecursiveInterconnect(1, ioAddrMap))
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mmioNetwork.io.in.head <> mmio
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val plic = Module(new PLIC(p(PLICKey)))
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val plic = Module(new PLIC(c.plicKey))
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plic.io.tl <> mmioNetwork.port("int:plic")
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for (i <- 0 until io.interrupts.size) {
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val gateway = Module(new LevelGateway)
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@ -191,25 +182,25 @@ class DefaultCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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tile.io.prci <> prci
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}
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for (i <- 0 until nTiles) {
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for (i <- 0 until tc.nTiles) {
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prci.io.interrupts(i).meip := plic.io.harts(plic.cfg.context(i, 'M'))
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if (p(UseVM))
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prci.io.interrupts(i).seip := plic.io.harts(plic.cfg.context(i, 'S'))
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prci.io.interrupts(i).debug := debugModule.io.debugInterrupts(i)
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}
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val tileSlavePorts = (0 until nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
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val tileSlavePorts = (0 until tc.nTiles) map (i => s"int:dmem$i") filter (ioAddrMap contains _)
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for ((t, m) <- (tileList.map(_.io.slave).flatten) zip (tileSlavePorts map (mmioNetwork port _)))
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t <> ClientUncachedTileLinkEnqueuer(m, 1)
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val bootROM = Module(new ROMSlave(makeBootROM()))
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bootROM.io <> mmioNetwork.port("int:bootrom")
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io.mmio.foreach { _ <> mmioNetwork.port("ext") }
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io.master.mmio.foreach { _ <> mmioNetwork.port("ext") }
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}
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}
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class GroundTestCoreplex(topParams: Parameters) extends DefaultCoreplex(topParams) {
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class GroundTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends DefaultCoreplex(tp, tc) {
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override def hasSuccessFlag = true
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io.success.get := tileList.flatMap(_.io.elements get "success").map(_.asInstanceOf[Bool]).reduce(_&&_)
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}
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@ -1,63 +0,0 @@
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package coreplex
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import Chisel._
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import cde.{Parameters, Field}
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import rocket.TileId
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import groundtest._
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import uncore.tilelink._
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import uncore.agents._
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case object ExportGroundTestStatus extends Field[Boolean]
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class DirectGroundTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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// Not using the debug
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io.debug.req.ready := Bool(false)
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io.debug.resp.valid := Bool(false)
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require(!exportMMIO)
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require(nExtClients == 0)
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require(nMemChannels == 1)
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require(nTiles == 1)
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val test = p(BuildGroundTest)(outermostParams.alterPartial({
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case TileId => 0
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case CacheName => "L1D"
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}))
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require(test.io.cache.size == 0)
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require(test.io.mem.size == nBanksPerMemChannel)
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require(test.io.ptw.size == 0)
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val mem_ic = Module(new TileLinkMemoryInterconnect(
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nBanksPerMemChannel, nMemChannels)(outermostParams))
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mem_ic.io.in <> test.io.mem
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io.mem <> mem_ic.io.out
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if (p(ExportGroundTestStatus)) {
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val status = io.extra.asInstanceOf[GroundTestStatus]
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val s_running :: s_finished :: s_errored :: s_timeout :: Nil = Enum(Bits(), 4)
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val state = Reg(init = s_running)
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val error_code = Reg(status.error.bits)
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val timeout_code = Reg(status.timeout.bits)
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when (state === s_running) {
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when (test.io.status.finished) { state := s_finished }
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when (test.io.status.error.valid) {
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state := s_errored
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error_code := test.io.status.error.bits
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}
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when (test.io.status.timeout.valid) {
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state := s_timeout
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timeout_code := test.io.status.timeout.bits
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}
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}
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status.finished := (state === s_finished)
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status.error.valid := (state === s_errored)
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status.error.bits := error_code
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status.timeout.valid := (state === s_timeout)
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status.timeout.bits := timeout_code
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}
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override def hasSuccessFlag = true
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io.success.get := test.io.status.finished
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}
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@ -2,6 +2,7 @@ package coreplex
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import Chisel._
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import groundtest._
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import rocketchip.{GlobalAddrMap}
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import rocket._
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import uncore.tilelink._
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import uncore.coherence._
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@ -24,7 +25,7 @@ class WithComparator extends Config(
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(p: Parameters) => Module(new ComparatorCore()(p))
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case ComparatorKey => ComparatorParameters(
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targets = Seq("mem", "io:ext:testram").map(name =>
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site(GlobalAddrMap)(name).start.longValue),
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site(GlobalAddrMap).get(name).start.longValue),
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width = 8,
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operations = 1000,
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atomics = site(UseAtomics),
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@ -54,7 +55,7 @@ class WithMemtest extends Config(
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}
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case GeneratorKey => GeneratorParameters(
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maxRequests = 128,
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startAddress = site(GlobalAddrMap)("mem").start)
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startAddress = site(GlobalAddrMap).get("mem").start)
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case BuildGroundTest =>
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(p: Parameters) => Module(new GeneratorTest()(p))
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case _ => throw new CDEMatchError
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@ -114,7 +115,7 @@ class WithNastiConverterTest extends Config(
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}
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case GeneratorKey => GeneratorParameters(
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maxRequests = 128,
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startAddress = site(GlobalAddrMap)("mem").start)
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startAddress = site(GlobalAddrMap).get("mem").start)
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case BuildGroundTest =>
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(p: Parameters) => Module(new NastiConverterTest()(p))
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case _ => throw new CDEMatchError
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@ -134,7 +135,7 @@ class WithTraceGen extends Config(
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val nSets = 32 // L2 NSets
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val nWays = 1
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val blockOffset = site(CacheBlockOffsetBits)
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val baseAddr = site(GlobalAddrMap)("mem").start
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val baseAddr = site(GlobalAddrMap).get("mem").start
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val nBeats = site(MIFDataBeats)
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List.tabulate(4 * nWays) { i =>
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Seq.tabulate(nBeats) { j => (j * 8) + ((i * nSets) << blockOffset) }
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@ -156,7 +157,7 @@ class WithPCIeMockupTest extends Config(
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GroundTestTileSettings(1))
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case GeneratorKey => GeneratorParameters(
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maxRequests = 128,
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startAddress = site(GlobalAddrMap)("mem").start)
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startAddress = site(GlobalAddrMap).get("mem").start)
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case BuildGroundTest =>
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(p: Parameters) => p(TileId) match {
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case 0 => Module(new GeneratorTest()(p))
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@ -6,9 +6,9 @@ import rocket.Tile
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import uncore.tilelink.TLId
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import cde.Parameters
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class UnitTestCoreplex(topParams: Parameters) extends Coreplex()(topParams) {
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require(!exportMMIO)
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require(nExtClients == 0)
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class UnitTestCoreplex(tp: Parameters, tc: CoreplexConfig) extends Coreplex()(tp, tc) {
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require(!tc.hasExtMMIOPort)
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require(tc.nSlaves == 0)
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require(nMemChannels == 0)
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io.debug.req.ready := Bool(false)
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