diff --git a/src/main/scala/junctions/hasti.scala b/src/main/scala/junctions/hasti.scala index 15eda989..8a6e4142 100644 --- a/src/main/scala/junctions/hasti.scala +++ b/src/main/scala/junctions/hasti.scala @@ -282,7 +282,10 @@ class HastiXbar(nMasters: Int, addressMap: Seq[UInt=>Bool])(implicit p: Paramete // However, if no slave is connected, for progress report ready anyway, if: // bad address (swallow request) OR idle (permit stupid masters to move FSM) val autoready = nowhereM(m) || masters(m).isIdle() - val hready = Mux1H(unionGrantMS(m), slaves.map(_.hready ^ autoready)) ^ autoready + val hready = if (nSlaves == 1) + Mux(unionGrantMS(m)(0), slaves(0).hready ^ autoready, Bool(false)) ^ autoready + else + Mux1H(unionGrantMS(m), slaves.map(_.hready ^ autoready)) ^ autoready masters(m).hready := hready // If we diverted a master, we need to absorb his address phase to replay later diversions(m).io.divert := (bubbleM(m) || blockedM(m)) && NSeq(m) && hready diff --git a/src/main/scala/uncore/ahb/Test.scala b/src/main/scala/uncore/ahb/Test.scala index 1c759fe3..a139b4bb 100644 --- a/src/main/scala/uncore/ahb/Test.scala +++ b/src/main/scala/uncore/ahb/Test.scala @@ -25,7 +25,7 @@ class AHBFuzzBridge()(implicit p: Parameters) extends LazyModule val gpio = LazyModule(new RRTest0(0x100)) model.node := fuzz.node - xbar.node := TLToAHB()(model.node) + xbar.node := TLToAHB()(TLDelayer(0.1)(model.node)) ram.node := xbar.node gpio.node := xbar.node diff --git a/src/main/scala/uncore/apb/Test.scala b/src/main/scala/uncore/apb/Test.scala index 960fd73d..e59c5820 100644 --- a/src/main/scala/uncore/apb/Test.scala +++ b/src/main/scala/uncore/apb/Test.scala @@ -25,7 +25,7 @@ class APBFuzzBridge()(implicit p: Parameters) extends LazyModule val gpio = LazyModule(new RRTest0(0x100)) model.node := fuzz.node - xbar.node := TLToAPB()(model.node) + xbar.node := TLToAPB()(TLDelayer(0.1)(model.node)) ram.node := xbar.node gpio.node := xbar.node diff --git a/src/main/scala/uncore/axi4/Test.scala b/src/main/scala/uncore/axi4/Test.scala index 2652b156..fb46cf9c 100644 --- a/src/main/scala/uncore/axi4/Test.scala +++ b/src/main/scala/uncore/axi4/Test.scala @@ -25,7 +25,7 @@ class AXI4LiteFuzzRAM()(implicit p: Parameters) extends LazyModule val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) model.node := fuzz.node - xbar.node := model.node + xbar.node := TLDelayer(0.1)(model.node) ram.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, true )(xbar.node)) gpio.node := AXI4Fragmenter(lite=true)(TLToAXI4(0, false)(xbar.node)) @@ -48,7 +48,7 @@ class AXI4FullFuzzRAM()(implicit p: Parameters) extends LazyModule val ram = LazyModule(new AXI4RAM(AddressSet(0x0, 0x3ff))) model.node := fuzz.node - xbar.node := model.node + xbar.node := TLDelayer(0.1)(model.node) ram.node := AXI4Fragmenter(lite=false, maxInFlight = 2)(TLToAXI4(4,false)(xbar.node)) gpio.node := AXI4Fragmenter(lite=false, maxInFlight = 5)(TLToAXI4(4,true )(xbar.node)) @@ -69,7 +69,7 @@ class AXI4FuzzMaster()(implicit p: Parameters) extends LazyModule val model = LazyModule(new TLRAMModel("AXI4FuzzMaster")) model.node := fuzz.node - node := TLToAXI4(4)(model.node) + node := TLToAXI4(4)(TLDelayer(0.1)(model.node)) lazy val module = new LazyModuleImp(this) { val io = new Bundle { diff --git a/src/main/scala/uncore/tilelink2/AsyncCrossing.scala b/src/main/scala/uncore/tilelink2/AsyncCrossing.scala index 5999cb9c..7736e7af 100644 --- a/src/main/scala/uncore/tilelink2/AsyncCrossing.scala +++ b/src/main/scala/uncore/tilelink2/AsyncCrossing.scala @@ -144,7 +144,7 @@ class TLRAMAsyncCrossing(implicit p: Parameters) extends LazyModule { val cross = LazyModule(new TLAsyncCrossing) model.node := fuzz.node - cross.node := TLFragmenter(4, 256)(model.node) + cross.node := TLFragmenter(4, 256)(TLDelayer(0.1)(model.node)) val monitor = (ram.node := cross.node) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { diff --git a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala index 1752a9fc..538b7565 100644 --- a/src/main/scala/uncore/tilelink2/AtomicAutomata.scala +++ b/src/main/scala/uncore/tilelink2/AtomicAutomata.scala @@ -299,7 +299,7 @@ class TLRAMAtomicAutomata()(implicit p: Parameters) extends LazyModule { val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) model.node := fuzz.node - ram.node := TLFragmenter(4, 256)(TLAtomicAutomata()(model.node)) + ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLAtomicAutomata()(TLDelayer(0.1)(model.node)))) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/uncore/tilelink2/Delayer.scala b/src/main/scala/uncore/tilelink2/Delayer.scala index 364d8320..06c1be76 100644 --- a/src/main/scala/uncore/tilelink2/Delayer.scala +++ b/src/main/scala/uncore/tilelink2/Delayer.scala @@ -19,19 +19,60 @@ class TLDelayer(q: Double)(implicit p: Parameters) extends LazyModule val out = node.bundleOut } - def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T]) { + def feed[T <: Data](sink: DecoupledIO[T], source: DecoupledIO[T], noise: T) { val allow = UInt((q * 65535.0).toInt) <= LFSR16(source.valid) sink.valid := source.valid && allow source.ready := sink.ready && allow sink.bits := source.bits + when (!sink.valid) { sink.bits := noise } } (io.in zip io.out) foreach { case (in, out) => - feed(out.a, in.a) - feed(out.c, in.c) - feed(out.e, in.e) - feed(in.b, out.b) - feed(in.d, out.d) + val anoise = Wire(in.a.bits) + anoise.opcode := LFSRNoiseMaker(3) + anoise.param := LFSRNoiseMaker(3) + anoise.size := LFSRNoiseMaker(anoise.params.sizeBits) + anoise.source := LFSRNoiseMaker(anoise.params.sourceBits) + anoise.address := LFSRNoiseMaker(anoise.params.addressBits) + anoise.mask := LFSRNoiseMaker(anoise.params.dataBits/8) + anoise.data := LFSRNoiseMaker(anoise.params.dataBits) + + val bnoise = Wire(out.b.bits) + bnoise.opcode := LFSRNoiseMaker(3) + bnoise.param := LFSRNoiseMaker(3) + bnoise.size := LFSRNoiseMaker(bnoise.params.sizeBits) + bnoise.source := LFSRNoiseMaker(bnoise.params.sourceBits) + bnoise.address := LFSRNoiseMaker(bnoise.params.addressBits) + bnoise.mask := LFSRNoiseMaker(bnoise.params.dataBits/8) + bnoise.data := LFSRNoiseMaker(bnoise.params.dataBits) + + val cnoise = Wire(in.c.bits) + cnoise.opcode := LFSRNoiseMaker(3) + cnoise.param := LFSRNoiseMaker(3) + cnoise.size := LFSRNoiseMaker(cnoise.params.sizeBits) + cnoise.source := LFSRNoiseMaker(cnoise.params.sourceBits) + cnoise.address := LFSRNoiseMaker(cnoise.params.addressBits) + cnoise.data := LFSRNoiseMaker(cnoise.params.dataBits) + cnoise.error := LFSRNoiseMaker(1)(0) + + val dnoise = Wire(out.d.bits) + dnoise.opcode := LFSRNoiseMaker(3) + dnoise.param := LFSRNoiseMaker(3) + dnoise.size := LFSRNoiseMaker(dnoise.params.sizeBits) + dnoise.source := LFSRNoiseMaker(dnoise.params.sourceBits) + dnoise.sink := LFSRNoiseMaker(dnoise.params.sinkBits) + dnoise.addr_lo := LFSRNoiseMaker(dnoise.params.addrLoBits) + dnoise.data := LFSRNoiseMaker(dnoise.params.dataBits) + dnoise.error := LFSRNoiseMaker(1)(0) + + val enoise = Wire(in.e.bits) + enoise.sink := LFSRNoiseMaker(enoise.params.sinkBits) + + feed(out.a, in.a, anoise) + feed(out.c, in.c, cnoise) + feed(out.e, in.e, enoise) + feed(in.b, out.b, bnoise) + feed(in.d, out.d, dnoise) } } } diff --git a/src/main/scala/uncore/tilelink2/Fragmenter.scala b/src/main/scala/uncore/tilelink2/Fragmenter.scala index 1b5a1538..b50ef19e 100644 --- a/src/main/scala/uncore/tilelink2/Fragmenter.scala +++ b/src/main/scala/uncore/tilelink2/Fragmenter.scala @@ -267,7 +267,7 @@ class TLRAMFragmenter(ramBeatBytes: Int, maxSize: Int)(implicit p: Parameters) e val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) model.node := fuzz.node - ram.node := TLFragmenter(ramBeatBytes, maxSize)(model.node) + ram.node := TLDelayer(0.1)(TLFragmenter(ramBeatBytes, maxSize)(TLDelayer(0.1)(model.node))) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/uncore/tilelink2/Fuzzer.scala b/src/main/scala/uncore/tilelink2/Fuzzer.scala index 724015f7..b186f232 100644 --- a/src/main/scala/uncore/tilelink2/Fuzzer.scala +++ b/src/main/scala/uncore/tilelink2/Fuzzer.scala @@ -34,18 +34,14 @@ class IDMapGenerator(numIds: Int) extends Module { object LFSR64 { - private var counter = 0 - private def next: Int = { - counter += 1 - counter - } - - def apply(increment: Bool = Bool(true), seed: Int = next): UInt = + def apply(increment: Bool = Bool(true)): UInt = { val wide = 64 - val lfsr = RegInit(UInt((seed * 0xDEADBEEFCAFEBAB1L) >>> 1, width = wide)) + val lfsr = Reg(UInt(width = wide)) // random initial value based on simulation seed val xor = lfsr(0) ^ lfsr(1) ^ lfsr(3) ^ lfsr(4) - when (increment) { lfsr := Cat(xor, lfsr(wide-1,1)) } + when (increment) { + lfsr := Mux(lfsr === UInt(0), UInt(1), Cat(xor, lfsr(wide-1,1))) + } lfsr } } diff --git a/src/main/scala/uncore/tilelink2/HintHandler.scala b/src/main/scala/uncore/tilelink2/HintHandler.scala index ff31beb5..0775aa52 100644 --- a/src/main/scala/uncore/tilelink2/HintHandler.scala +++ b/src/main/scala/uncore/tilelink2/HintHandler.scala @@ -116,7 +116,7 @@ class TLRAMHintHandler()(implicit p: Parameters) extends LazyModule { val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) model.node := fuzz.node - ram.node := TLFragmenter(4, 256)(TLHintHandler()(model.node)) + ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(TLHintHandler()(TLDelayer(0.1)(model.node)))) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala index 5bef9428..febf91cd 100644 --- a/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala +++ b/src/main/scala/uncore/tilelink2/RegisterRouterTest.scala @@ -259,7 +259,7 @@ class FuzzRRTest0()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val rrtr = LazyModule(new RRTest0(0x400)) - rrtr.node := TLFragmenter(4, 32)(TLBuffer()(fuzz.node)) + rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node)) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { io.finished := fuzz.module.io.finished @@ -274,7 +274,7 @@ class FuzzRRTest1()(implicit p: Parameters) extends LazyModule { val fuzz = LazyModule(new TLFuzzer(5000)) val rrtr = LazyModule(new RRTest1(0x400)) - rrtr.node := TLFragmenter(4, 32)(TLBuffer()(fuzz.node)) + rrtr.node := TLFragmenter(4, 32)(TLDelayer(0.1)(fuzz.node)) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/uncore/tilelink2/SRAM.scala b/src/main/scala/uncore/tilelink2/SRAM.scala index fcf611d4..d287c094 100644 --- a/src/main/scala/uncore/tilelink2/SRAM.scala +++ b/src/main/scala/uncore/tilelink2/SRAM.scala @@ -95,7 +95,7 @@ class TLRAMSimple(ramBeatBytes: Int)(implicit p: Parameters) extends LazyModule val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff), beatBytes = ramBeatBytes)) model.node := fuzz.node - ram.node := model.node + ram.node := TLDelayer(0.25)(model.node) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/uncore/tilelink2/WidthWidget.scala b/src/main/scala/uncore/tilelink2/WidthWidget.scala index f431cc31..e066722a 100644 --- a/src/main/scala/uncore/tilelink2/WidthWidget.scala +++ b/src/main/scala/uncore/tilelink2/WidthWidget.scala @@ -180,11 +180,11 @@ class TLRAMWidthWidget(first: Int, second: Int)(implicit p: Parameters) extends val ram = LazyModule(new TLRAM(AddressSet(0x0, 0x3ff))) model.node := fuzz.node - ram.node := TLFragmenter(4, 256)( - if (first == second ) { TLWidthWidget(first)(model.node) } + ram.node := TLDelayer(0.1)(TLFragmenter(4, 256)( + if (first == second ) { TLWidthWidget(first)(TLDelayer(0.1)(model.node)) } else { TLWidthWidget(second)( - TLWidthWidget(first)(model.node))}) + TLWidthWidget(first)(TLDelayer(0.1)(model.node)))})) lazy val module = new LazyModuleImp(this) with HasUnitTestIO { io.finished := fuzz.module.io.finished diff --git a/src/main/scala/uncore/tilelink2/Xbar.scala b/src/main/scala/uncore/tilelink2/Xbar.scala index a030c8ef..f7cc2e62 100644 --- a/src/main/scala/uncore/tilelink2/Xbar.scala +++ b/src/main/scala/uncore/tilelink2/Xbar.scala @@ -191,10 +191,10 @@ class TLRAMXbar(nManagers: Int)(implicit p: Parameters) extends LazyModule { val xbar = LazyModule(new TLXbar) model.node := fuzz.node - xbar.node := model.node + xbar.node := TLDelayer(0.1)(model.node) (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) - ram.node := TLFragmenter(4, 256)(xbar.node) + ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node)) } lazy val module = new LazyModuleImp(this) with HasUnitTestIO { @@ -211,13 +211,13 @@ class TLMulticlientXbar(nManagers: Int, nClients: Int)(implicit p: Parameters) e val fuzzers = (0 until nClients) map { n => val fuzz = LazyModule(new TLFuzzer(5000)) - xbar.node := fuzz.node + xbar.node := TLDelayer(0.1)(fuzz.node) fuzz } (0 until nManagers) foreach { n => val ram = LazyModule(new TLRAM(AddressSet(0x0+0x400*n, 0x3ff))) - ram.node := TLFragmenter(4, 256)(xbar.node) + ram.node := TLFragmenter(4, 256)(TLDelayer(0.1)(xbar.node)) } lazy val module = new LazyModuleImp(this) with HasUnitTestIO {