From bac82762d354316fedaf4e4c23902a4c739ac7c6 Mon Sep 17 00:00:00 2001 From: Andrew Waterman Date: Thu, 12 Jul 2012 14:50:12 -0700 Subject: [PATCH] use only one (wide) tag ram for set assoc. caches --- rocket/src/main/scala/icache.scala | 36 +++++++++--------- rocket/src/main/scala/nbdcache.scala | 57 ++++++++++------------------ 2 files changed, 39 insertions(+), 54 deletions(-) diff --git a/rocket/src/main/scala/icache.scala b/rocket/src/main/scala/icache.scala index 3f627f77..5318ce7a 100644 --- a/rocket/src/main/scala/icache.scala +++ b/rocket/src/main/scala/icache.scala @@ -92,32 +92,32 @@ class rocketICache(sets: Int, assoc: Int, co: CoherencePolicyWithUncached) exten Mux((state === s_refill_wait) || (state === s_refill), Cat(r_cpu_req_idx(indexmsb,offsetbits), refill_count), io.cpu.req_idx(indexmsb, offsetbits-rf_cnt_bits)).toUFix; + val tag_array = Mem(sets, seqRead = true) { Bits(width = tagbits*assoc) } + val tag_rdata = Reg() { Bits() } + when (tag_we) { + tag_array.write(tag_addr, Fill(assoc, r_cpu_miss_tag), FillInterleaved(tagbits, if (assoc > 1) UFixToOH(repl_way) else Bits(1))) + }.otherwise { + tag_rdata := tag_array(tag_addr) + } + + val vb_array = Reg(resetVal = Bits(0, lines)) + when (io.cpu.invalidate) { + vb_array := Bits(0) + }.elsewhen (tag_we) { + vb_array := vb_array.bitSet(Cat(r_cpu_req_idx(indexmsb,indexlsb), if (assoc > 1) repl_way else null), !invalidated) + } + val data_mux = (new Mux1H(assoc)){Bits(width = databits)} var any_hit = Bool(false) for (i <- 0 until assoc) { - val repl_me = (repl_way === UFix(i)) - val tag_array = Mem(sets, seqRead = true){ Bits(width = tagbits) } - val tag_rdata = Reg() { Bits(width = tagbits) } - when (tag_we && repl_me) { tag_array(tag_addr) := r_cpu_miss_tag } - .otherwise { tag_rdata := tag_array(tag_addr) } - - // valid bit array - val vb_array = Reg(resetVal = Bits(0, sets)); - when (io.cpu.invalidate) { - vb_array := Bits(0) - } - .elsewhen (tag_we && repl_me) { - vb_array := vb_array.bitSet(r_cpu_req_idx(indexmsb,indexlsb).toUFix, !invalidated) - } - - val valid = vb_array(r_cpu_req_idx(indexmsb,indexlsb)).toBool; - val hit = valid && (tag_rdata === r_cpu_hit_addr(tagmsb,taglsb)) + val valid = vb_array(Cat(r_cpu_req_idx(indexmsb,indexlsb), if (assoc > 1) UFix(i, log2Up(assoc)) else null)) + val hit = valid && tag_rdata(tagbits*(i+1)-1, tagbits*i) === r_cpu_hit_addr(tagmsb,taglsb) // data array val data_array = Mem(sets*REFILL_CYCLES, seqRead = true){ io.mem.xact_rep.bits.data.clone } val data_out = Reg(){ io.mem.xact_rep.bits.data.clone } - when (io.mem.xact_rep.valid && repl_me) { data_array(data_addr) := io.mem.xact_rep.bits.data } + when (io.mem.xact_rep.valid && repl_way === UFix(i)) { data_array(data_addr) := io.mem.xact_rep.bits.data } .otherwise { data_out := data_array(data_addr) } data_mux.io.sel(i) := hit diff --git a/rocket/src/main/scala/nbdcache.scala b/rocket/src/main/scala/nbdcache.scala index 1a0977c8..fdc7376a 100644 --- a/rocket/src/main/scala/nbdcache.scala +++ b/rocket/src/main/scala/nbdcache.scala @@ -595,35 +595,6 @@ class FlushUnit(lines: Int, co: CoherencePolicy) extends Component { io.meta_req.bits.data.tag := UFix(0) } -class MetaDataArray(lines: Int) extends Component { - val io = new Bundle { - val req = (new FIFOIO) { new MetaArrayReq() }.flip - val resp = (new MetaData).asOutput() - val state_req = (new FIFOIO) { new MetaArrayReq() }.flip - } - - val permissions_array = Mem(lines){ UFix(width = 2) } - val raddr = Reg() { Bits() } - when (io.state_req.valid && io.state_req.bits.rw) { - permissions_array(io.state_req.bits.idx) := io.state_req.bits.data.state - } - when (io.req.valid) { - when (io.req.bits.rw) { permissions_array(io.req.bits.idx) := io.req.bits.data.state } - .otherwise { raddr := io.req.bits.idx } - } - - val tag_array = Mem(lines, seqRead = true){ Bits(width=TAG_BITS) } - val tag_rdata = Reg() { Bits() } - when (io.req.valid) { - when (io.req.bits.rw) { tag_array(io.req.bits.idx) := io.req.bits.data.tag } - .otherwise { tag_rdata := tag_array(io.req.bits.idx) } - } - - io.resp.state := permissions_array(raddr) - io.resp.tag := tag_rdata - io.req.ready := Bool(true) -} - class MetaDataArrayArray(lines: Int) extends Component { val io = new Bundle { val req = (new FIFOIO) { new MetaArrayReq() }.flip @@ -632,18 +603,32 @@ class MetaDataArrayArray(lines: Int) extends Component { val way_en = Bits(width = NWAYS, dir = OUTPUT) } + val permBits = io.req.bits.data.state.width + val perms = Mem(lines) { UFix(width = permBits*NWAYS) } + val tags = Mem(lines*NWAYS, seqRead = true) { Bits(width = TAG_BITS*NWAYS) } + val tag = Reg() { Bits() } + val raddr = Reg() { Bits() } val way_en_ = Reg { Bits(width=NWAYS) } - when (io.req.valid && io.req.ready) { + + when (io.state_req.valid && io.state_req.bits.rw) { + perms.write(io.state_req.bits.idx, Fill(NWAYS, io.state_req.bits.data.state), FillInterleaved(permBits, io.state_req.bits.way_en)) + } + when (io.req.valid) { + when (io.req.bits.rw) { + perms.write(io.req.bits.idx, Fill(NWAYS, io.req.bits.data.state), FillInterleaved(permBits, io.req.bits.way_en)) + tags.write(io.req.bits.idx, Fill(NWAYS, io.req.bits.data.tag), FillInterleaved(TAG_BITS, io.req.bits.way_en)) + } + .otherwise { + raddr := io.req.bits.idx + tag := tags(io.req.bits.idx) + } way_en_ := io.req.bits.way_en } + val perm = perms(raddr) for(w <- 0 until NWAYS) { - val way = new MetaDataArray(lines) - way.io.req.bits <> io.req.bits - way.io.req.valid := io.req.valid && io.req.bits.way_en(w).toBool - way.io.state_req.bits <> io.state_req.bits - way.io.state_req.valid := io.state_req.valid && io.state_req.bits.way_en(w).toBool - way.io.resp <> io.resp(w) + io.resp(w).state := perm(permBits*(w+1)-1, permBits*w) + io.resp(w).tag := tag(TAG_BITS*(w+1)-1, TAG_BITS*w) } io.way_en := way_en_