TileLink refactor; TileLinkPorts now available. L2Banks no longer have unique ids (suitable for hierarhical P&R).
This commit is contained in:
Henry Cook
@ -23,12 +23,14 @@ case object TLDataBits extends Field[Int]
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case object TLDataBeats extends Field[Int]
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case object TLNetworkIsOrderedP2P extends Field[Boolean]
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abstract trait TileLinkParameters extends UsesParameters {
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trait TileLinkParameters extends UsesParameters {
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val tlCoh = params(TLCoherencePolicy)
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val tlNManagers = params(TLNManagers)
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val tlNClients = params(TLNClients)
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val tlNCoherentClients = params(TLNCoherentClients)
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val tlNIncoherentClients = params(TLNIncoherentClients)
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val tlClientIdBits = log2Up(tlNClients)
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val tlManagerIdBits = log2Up(tlNManagers)
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val tlMaxClientXacts = params(TLMaxClientXacts)
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val tlMaxClientPorts = params(TLMaxClientPorts)
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val tlMaxManagerXacts = params(TLMaxManagerXacts)
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@ -98,6 +100,10 @@ trait HasTileLinkData extends HasTileLinkBeatId {
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def hasMultibeatData(dummy: Int = 0): Bool
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}
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trait HasClientId extends TLBundle {
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val client_id = UInt(width = tlClientIdBits)
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}
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// Actual TileLink channel bundle definitions
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class Acquire extends ClientToManagerChannel
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@ -350,12 +356,19 @@ class Probe extends ManagerToClientChannel
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}
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object Probe {
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def apply(p_type: UInt, addr_block: UInt) = {
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def apply(p_type: UInt, addr_block: UInt): Probe = {
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val prb = new Probe
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prb.p_type := p_type
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prb.addr_block := addr_block
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prb
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}
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def apply(dst: UInt, p_type: UInt, addr_block: UInt): ProbeToDst = {
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val prb = new ProbeToDst
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prb.client_id := dst
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prb.p_type := p_type
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prb.addr_block := addr_block
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prb
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}
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}
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class Release extends ClientToManagerChannel
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@ -435,8 +448,8 @@ object Grant {
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g_type: UInt,
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client_xact_id: UInt,
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manager_xact_id: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): Grant = {
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addr_beat: UInt,
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data: UInt): Grant = {
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val gnt = new Grant
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gnt.is_builtin_type := is_builtin_type
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gnt.g_type := g_type
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@ -446,6 +459,25 @@ object Grant {
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gnt.data := data
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gnt
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}
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def apply(
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dst: UInt,
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is_builtin_type: Bool,
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g_type: UInt,
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client_xact_id: UInt,
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manager_xact_id: UInt,
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addr_beat: UInt = UInt(0),
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data: UInt = UInt(0)): GrantToDst = {
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val gnt = new GrantToDst
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gnt.client_id := dst
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gnt.is_builtin_type := is_builtin_type
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gnt.g_type := g_type
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gnt.client_xact_id := client_xact_id
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gnt.manager_xact_id := manager_xact_id
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gnt.addr_beat := addr_beat
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gnt.data := data
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gnt
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}
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}
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class Finish extends ClientToManagerChannel with HasManagerTransactionId {
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@ -453,7 +485,14 @@ class Finish extends ClientToManagerChannel with HasManagerTransactionId {
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def hasMultibeatData(dummy: Int = 0) = Bool(false)
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}
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// Complete IO definitions for two types of TileLink clients
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// These subtypes include a field for the source or destination ClientId
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class AcquireFromSrc extends Acquire with HasClientId
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class ProbeToDst extends Probe with HasClientId
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class ReleaseFromSrc extends Release with HasClientId
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class GrantToDst extends Grant with HasClientId
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// Complete IO definitions for two types of TileLink clients, including
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// networking headers
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class UncachedTileLinkIO extends TLBundle {
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val acquire = new DecoupledIO(new LogicalNetworkIO(new Acquire))
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val grant = new DecoupledIO(new LogicalNetworkIO(new Grant)).flip
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@ -479,28 +518,36 @@ class TileLinkIOWrapper extends TLModule {
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io.out.release.valid := Bool(false)
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}
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// This version of TileLinkIO does not contain network headers for packets
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// that originate in the Clients (i.e. Acquire and Release). These headers
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// are provided in the top-level that instantiates the clients and network.
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// This version of TileLinkIO does not contain network headers. The headers
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// are provided in the top-level that instantiates the clients and network,
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// probably using a TileLinkClientPort module.
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// By eliding the header subbundles within the clients we can enable
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// hierarchical P&R while minimizing unconnected port errors in GDS.
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// Secondly, this version of the interface elides Finish messages, with the
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// assumption that a FinishUnit has been coupled to the TileLinkIO port
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// to deal with acking received Grants.
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class HeaderlessUncachedTileLinkIO extends TLBundle {
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class ClientUncachedTileLinkIO extends TLBundle {
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val acquire = new DecoupledIO(new Acquire)
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val grant = new DecoupledIO(new Grant).flip
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}
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class HeaderlessTileLinkIO extends HeaderlessUncachedTileLinkIO {
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class ClientTileLinkIO extends ClientUncachedTileLinkIO {
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val probe = new DecoupledIO(new Probe).flip
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val release = new DecoupledIO(new Release)
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}
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class HeaderlessTileLinkIOWrapper extends TLModule {
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class ManagerTileLinkIO extends TLBundle {
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val acquire = new DecoupledIO(new AcquireFromSrc).flip
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val grant = new DecoupledIO(new GrantToDst)
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val finish = new DecoupledIO(new Finish).flip
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val probe = new DecoupledIO(new ProbeToDst)
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val release = new DecoupledIO(new ReleaseFromSrc).flip
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}
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class ClientTileLinkIOWrapper extends TLModule {
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val io = new Bundle {
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val in = new HeaderlessUncachedTileLinkIO().flip
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val out = new HeaderlessTileLinkIO
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val in = new ClientUncachedTileLinkIO().flip
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val out = new ClientTileLinkIO
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}
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io.out.acquire <> io.in.acquire
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io.out.grant <> io.in.grant
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@ -509,17 +556,17 @@ class HeaderlessTileLinkIOWrapper extends TLModule {
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}
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object TileLinkIOWrapper {
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def apply(utl: HeaderlessUncachedTileLinkIO, p: Parameters): HeaderlessTileLinkIO = {
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val conv = Module(new HeaderlessTileLinkIOWrapper)(p)
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def apply(utl: ClientUncachedTileLinkIO, p: Parameters): ClientTileLinkIO = {
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val conv = Module(new ClientTileLinkIOWrapper)(p)
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conv.io.in <> utl
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conv.io.out
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}
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def apply(utl: HeaderlessUncachedTileLinkIO): HeaderlessTileLinkIO = {
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val conv = Module(new HeaderlessTileLinkIOWrapper)
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def apply(utl: ClientUncachedTileLinkIO): ClientTileLinkIO = {
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val conv = Module(new ClientTileLinkIOWrapper)
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conv.io.in <> utl
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conv.io.out
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}
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def apply(tl: HeaderlessTileLinkIO): HeaderlessTileLinkIO = tl
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def apply(tl: ClientTileLinkIO): ClientTileLinkIO = tl
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def apply(utl: UncachedTileLinkIO, p: Parameters): TileLinkIO = {
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val conv = Module(new TileLinkIOWrapper)(p)
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conv.io.in <> utl
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@ -533,89 +580,6 @@ object TileLinkIOWrapper {
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def apply(tl: TileLinkIO): TileLinkIO = tl
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}
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trait HasDataBeatCounters {
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type HasBeat = TileLinkChannel with HasTileLinkBeatId
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type HasClientId = TileLinkChannel with HasClientTransactionId
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type LNAcquire = LogicalNetworkIO[Acquire]
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type LNRelease = LogicalNetworkIO[Release]
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type LNGrant = LogicalNetworkIO[Grant]
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def connectDataBeatCounter[S <: TileLinkChannel : ClassTag](inc: Bool, data: S, beat: UInt) = {
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val multi = data.hasMultibeatData()
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val (multi_cnt, multi_done) = Counter(inc && multi, data.tlDataBeats)
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val cnt = Mux(multi, multi_cnt, beat)
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val done = Mux(multi, multi_done, inc)
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(cnt, done)
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}
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def connectOutgoingDataBeatCounter[T <: Data : TypeTag](
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in: DecoupledIO[T],
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beat: UInt = UInt(0)): (UInt, Bool) = {
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in.bits match {
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case p: TileLinkChannel if typeTag[T].tpe <:< typeTag[TileLinkChannel].tpe =>
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connectDataBeatCounter(in.fire(), p, beat)
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case ln: LNGrant if typeTag[T].tpe <:< typeTag[LNGrant].tpe =>
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connectDataBeatCounter(in.fire(), ln.payload, beat)
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case _ => { require(false, "Don't know how to connect a beat counter to " + typeTag[T].tpe); (UInt(0), Bool(false))}
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}
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}
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def connectIncomingDataBeatCounters[T <: HasClientId : ClassTag](
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in: DecoupledIO[LogicalNetworkIO[T]],
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entries: Int,
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getId: LogicalNetworkIO[T] => UInt): Vec[Bool] = {
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Vec((0 until entries).map { i =>
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connectDataBeatCounter(in.fire() && getId(in.bits) === UInt(i), in.bits.payload, UInt(0))._2
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})
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}
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def connectIncomingDataBeatCounter[T <: Data : TypeTag](in: DecoupledIO[T]): Bool = {
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in.bits match {
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case p: TileLinkChannel if typeTag[T].tpe <:< typeTag[TileLinkChannel].tpe =>
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connectDataBeatCounter(in.fire(), p, UInt(0))._2
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case ln: LNAcquire if typeTag[T].tpe =:= typeTag[LNAcquire].tpe =>
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connectDataBeatCounter(in.fire(), ln.payload, UInt(0))._2
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case ln: LNRelease if typeTag[T].tpe =:= typeTag[LNRelease].tpe =>
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connectDataBeatCounter(in.fire(), ln.payload, UInt(0))._2
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case ln: LNGrant if typeTag[T].tpe =:= typeTag[LNGrant].tpe =>
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connectDataBeatCounter(in.fire(), ln.payload, UInt(0))._2
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case _ => { require(false, "Don't know how to connect a beat counter to " + typeTag[T].tpe); Bool(false)}
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}
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}
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def connectHeaderlessTwoWayBeatCounter[ T <: TileLinkChannel : ClassTag, S <: TileLinkChannel : ClassTag](
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max: Int,
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up: DecoupledIO[T],
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down: DecoupledIO[S],
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beat: UInt): (Bool, UInt, Bool, UInt, Bool) = {
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val cnt = Reg(init = UInt(0, width = log2Up(max+1)))
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val (up_idx, do_inc) = connectDataBeatCounter(up.fire(), up.bits, beat)
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val (down_idx, do_dec) = connectDataBeatCounter(down.fire(), down.bits, beat)
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//Module.assert(!(do_dec && cnt === UInt(0)), "Decrementing 2way beat counter before ever incrementing")
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cnt := Mux(do_dec,
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Mux(do_inc, cnt, cnt - UInt(1)),
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Mux(do_inc, cnt + UInt(1), cnt))
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(cnt > UInt(0), up_idx, do_inc, down_idx, do_dec)
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}
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def connectTwoWayBeatCounter[ T <: TileLinkChannel : ClassTag, S <: TileLinkChannel : ClassTag](
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max: Int,
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up: DecoupledIO[LogicalNetworkIO[T]],
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down: DecoupledIO[LogicalNetworkIO[S]],
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inc: T => Bool = (t: T) => Bool(true),
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dec: S => Bool = (s: S) => Bool(true)): (Bool, UInt, Bool, UInt, Bool) = {
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val cnt = Reg(init = UInt(0, width = log2Up(max+1)))
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val (up_idx, up_done) = connectDataBeatCounter(up.fire(), up.bits.payload, UInt(0))
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val (down_idx, down_done) = connectDataBeatCounter(down.fire(), down.bits.payload, UInt(0))
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val do_inc = up_done && inc(up.bits.payload)
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val do_dec = down_done && dec(down.bits.payload)
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cnt := Mux(do_dec,
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Mux(do_inc, cnt, cnt - UInt(1)),
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Mux(do_inc, cnt + UInt(1), cnt))
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(cnt > UInt(0), up_idx, up_done, down_idx, down_done)
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}
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}
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class FinishQueueEntry extends TLBundle {
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val fin = new Finish
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val dst = UInt(width = log2Up(params(LNEndpoints)))
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@ -623,8 +587,7 @@ class FinishQueueEntry extends TLBundle {
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class FinishQueue(entries: Int) extends Queue(new FinishQueueEntry, entries)
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class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule
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with HasDataBeatCounters {
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class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule with HasDataBeatCounters {
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val io = new Bundle {
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val grant = Decoupled(new LogicalNetworkIO(new Grant)).flip
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val refill = Decoupled(new Grant)
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@ -645,12 +608,12 @@ class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule
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// a multibeat Grant. But Grants from multiple managers or transactions may
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// get interleaved, so we could need a counter for each.
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val done = if(tlNetworkDoesNotInterleaveBeats) {
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connectIncomingDataBeatCounter(io.grant)
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connectIncomingDataBeatCounterWithHeader(io.grant)
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} else {
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val entries = 1 << tlClientXactIdBits
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def getId(g: LogicalNetworkIO[Grant]) = g.payload.client_xact_id
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assert(getId(io.grant.bits) <= UInt(entries), "Not enough grant beat counters, only " + entries + " entries.")
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connectIncomingDataBeatCounters(io.grant, entries, getId).reduce(_||_)
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connectIncomingDataBeatCountersWithHeader(io.grant, entries, getId).reduce(_||_)
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}
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val q = Module(new FinishQueue(outstanding))
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q.io.enq.valid := io.grant.fire() && g.requiresAck() && (!g.hasMultibeatData() || done)
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@ -670,30 +633,7 @@ class FinishUnit(srcId: Int = 0, outstanding: Int = 2) extends TLModule
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}
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}
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object TileLinkHeaderOverwriter {
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def apply[T <: ClientToManagerChannel](
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in: DecoupledIO[LogicalNetworkIO[T]],
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clientId: Int,
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passThrough: Boolean): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = in.clone.asDirectionless
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out.bits.payload := in.bits.payload
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out.bits.header.src := UInt(clientId)
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out.bits.header.dst := (if(passThrough) in.bits.header.dst else UInt(0))
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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def apply[T <: ClientToManagerChannel with HasCacheBlockAddress](
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in: DecoupledIO[LogicalNetworkIO[T]],
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clientId: Int,
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nBanks: Int,
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addrConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
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val out: DecoupledIO[LogicalNetworkIO[T]] = apply(in, clientId, false)
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out.bits.header.dst := addrConvert(in.bits.payload.addr_block)
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out
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}
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object ClientTileLinkHeaderCreator {
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def apply[T <: ClientToManagerChannel with HasCacheBlockAddress : ClassTag](
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in: DecoupledIO[T],
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clientId: Int,
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@ -708,9 +648,24 @@ object TileLinkHeaderOverwriter {
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}
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}
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class TileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extends TLModule {
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object ManagerTileLinkHeaderCreator {
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def apply[T <: ManagerToClientChannel with HasClientId : ClassTag](
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in: DecoupledIO[T],
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managerId: Int,
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idConvert: UInt => UInt): DecoupledIO[LogicalNetworkIO[T]] = {
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val out = new DecoupledIO(new LogicalNetworkIO(in.bits.clone)).asDirectionless
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out.bits.payload := in.bits
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out.bits.header.src := UInt(managerId)
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out.bits.header.dst := idConvert(in.bits.client_id)
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out.valid := in.valid
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in.ready := out.ready
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out
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}
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}
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class ClientTileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extends TLModule {
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val io = new Bundle {
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val client = new HeaderlessTileLinkIO().flip
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val client = new ClientTileLinkIO().flip
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val network = new TileLinkIO
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}
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@ -718,8 +673,8 @@ class TileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extends TLMo
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finisher.io.grant <> io.network.grant
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io.network.finish <> finisher.io.finish
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val acq_with_header = TileLinkHeaderOverwriter(io.client.acquire, clientId, addrConvert)
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val rel_with_header = TileLinkHeaderOverwriter(io.client.release, clientId, addrConvert)
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val acq_with_header = ClientTileLinkHeaderCreator(io.client.acquire, clientId, addrConvert)
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val rel_with_header = ClientTileLinkHeaderCreator(io.client.release, clientId, addrConvert)
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val prb_without_header = DecoupledLogicalNetworkIOUnwrapper(io.network.probe)
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val gnt_without_header = finisher.io.refill
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@ -731,58 +686,63 @@ class TileLinkNetworkPort(clientId: Int, addrConvert: UInt => UInt) extends TLMo
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io.client.grant <> gnt_without_header
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}
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object TileLinkNetworkPort {
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def apply[T <: Data](
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client: HeaderlessTileLinkIO,
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clientId: Int = 0,
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addrConvert: UInt => UInt = u => UInt(0))(implicit p: Parameters): TileLinkIO = {
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val port = Module(new TileLinkNetworkPort(clientId, addrConvert))(p)
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port.io.client <> client
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port.io.network
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class ManagerTileLinkNetworkPort(managerId: Int, idConvert: UInt => UInt) extends TLModule {
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val io = new Bundle {
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val manager = new ManagerTileLinkIO().flip
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val network = new TileLinkIO().flip
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}
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io.network.grant <> ManagerTileLinkHeaderCreator(io.manager.grant, managerId, (u: UInt) => u)
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io.network.probe <> ManagerTileLinkHeaderCreator(io.manager.probe, managerId, idConvert)
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io.manager.acquire.bits.client_id := io.network.acquire.bits.header.src
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io.manager.acquire <> DecoupledLogicalNetworkIOUnwrapper(io.network.acquire)
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io.manager.release.bits.client_id := io.network.release.bits.header.src
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io.manager.release <> DecoupledLogicalNetworkIOUnwrapper(io.network.release)
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io.manager.finish <> DecoupledLogicalNetworkIOUnwrapper(io.network.finish)
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}
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class TileLinkEnqueuer(depths: (Int, Int, Int, Int, Int)) extends Module {
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case class TileLinkDepths(acq: Int, prb: Int, rel: Int, gnt: Int, fin: Int)
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class TileLinkEnqueuer(depths: TileLinkDepths) extends Module {
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val io = new Bundle {
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val client = new TileLinkIO().flip
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val manager = new TileLinkIO
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}
|
||||
io.manager.acquire <> (if(depths._1 > 0) Queue(io.client.acquire, depths._1) else io.client.acquire)
|
||||
io.client.probe <> (if(depths._2 > 0) Queue(io.manager.probe, depths._2) else io.manager.probe)
|
||||
io.manager.release <> (if(depths._3 > 0) Queue(io.client.release, depths._3) else io.client.release)
|
||||
io.client.grant <> (if(depths._4 > 0) Queue(io.manager.grant, depths._4) else io.manager.grant)
|
||||
io.manager.finish <> (if(depths._5 > 0) Queue(io.client.finish, depths._5) else io.client.finish)
|
||||
io.manager.acquire <> (if(depths.acq > 0) Queue(io.client.acquire, depths.acq) else io.client.acquire)
|
||||
io.client.probe <> (if(depths.prb > 0) Queue(io.manager.probe, depths.prb) else io.manager.probe)
|
||||
io.manager.release <> (if(depths.rel > 0) Queue(io.client.release, depths.rel) else io.client.release)
|
||||
io.client.grant <> (if(depths.gnt > 0) Queue(io.manager.grant, depths.gnt) else io.manager.grant)
|
||||
io.manager.finish <> (if(depths.fin > 0) Queue(io.client.finish, depths.fin) else io.client.finish)
|
||||
}
|
||||
|
||||
object TileLinkEnqueuer {
|
||||
def apply(in: TileLinkIO, depths: (Int, Int, Int, Int, Int))(p: Parameters): TileLinkIO = {
|
||||
def apply(in: TileLinkIO, depths: TileLinkDepths)(p: Parameters): TileLinkIO = {
|
||||
val t = Module(new TileLinkEnqueuer(depths))(p)
|
||||
t.io.client <> in
|
||||
t.io.manager
|
||||
}
|
||||
def apply(in: TileLinkIO, depth: Int)(p: Parameters): TileLinkIO = {
|
||||
apply(in, (depth, depth, depth, depth, depth))(p)
|
||||
apply(in, TileLinkDepths(depth, depth, depth, depth, depth))(p)
|
||||
}
|
||||
}
|
||||
|
||||
abstract trait HasArbiterTypes {
|
||||
/** Utility functions for constructing TileLinkIO arbiters */
|
||||
trait TileLinkArbiterLike extends TileLinkParameters {
|
||||
// Some shorthand type variables
|
||||
type ManagerSourcedWithId = ManagerToClientChannel with HasClientTransactionId
|
||||
type ClientSourcedWithId = ClientToManagerChannel with HasClientTransactionId
|
||||
type ClientSourcedWithIdAndData = ClientToManagerChannel with
|
||||
HasClientTransactionId with
|
||||
HasTileLinkData
|
||||
}
|
||||
type ClientSourcedWithIdAndData = ClientToManagerChannel with HasClientTransactionId with HasTileLinkData
|
||||
|
||||
// Utility functions for constructing TileLinkIO arbiters
|
||||
trait TileLinkArbiterLike extends HasArbiterTypes with TileLinkParameters{
|
||||
val arbN: Int
|
||||
// These are filled in depending on whether the arbiter mucks with the
|
||||
// client ids and then needs to revert them on the way back
|
||||
val arbN: Int // The number of ports on the client side
|
||||
|
||||
// These abstract funcs are filled in depending on whether the arbiter mucks with the
|
||||
// outgoing client ids to track sourcing and then needs to revert them on the way back
|
||||
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int): Bits
|
||||
def managerSourcedClientXactId(in: ManagerSourcedWithId): Bits
|
||||
def arbIdx(in: ManagerSourcedWithId): UInt
|
||||
|
||||
def hookupClientSource[M <: ClientSourcedWithIdAndData : ClassTag](
|
||||
// The following functions are all wiring helpers for each of the different types of TileLink channels
|
||||
|
||||
def hookupClientSource[M <: ClientSourcedWithIdAndData](
|
||||
clts: Seq[DecoupledIO[LogicalNetworkIO[M]]],
|
||||
mngr: DecoupledIO[LogicalNetworkIO[M]]) {
|
||||
def hasData(m: LogicalNetworkIO[M]) = m.payload.hasMultibeatData()
|
||||
@ -796,7 +756,7 @@ trait TileLinkArbiterLike extends HasArbiterTypes with TileLinkParameters{
|
||||
arb.io.out <> mngr
|
||||
}
|
||||
|
||||
def hookupClientSourceHeaderless[M <: ClientSourcedWithIdAndData : ClassTag](
|
||||
def hookupClientSourceHeaderless[M <: ClientSourcedWithIdAndData](
|
||||
clts: Seq[DecoupledIO[M]],
|
||||
mngr: DecoupledIO[M]) {
|
||||
def hasData(m: M) = m.hasMultibeatData()
|
||||
@ -854,23 +814,20 @@ trait TileLinkArbiterLike extends HasArbiterTypes with TileLinkParameters{
|
||||
}
|
||||
}
|
||||
|
||||
def hookupManagerSourceBroadcast[M <: Data](
|
||||
clts: Seq[DecoupledIO[M]],
|
||||
mngr: DecoupledIO[M]) {
|
||||
def hookupManagerSourceBroadcast[M <: Data](clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]) {
|
||||
clts.map{ _.valid := mngr.valid }
|
||||
clts.map{ _.bits := mngr.bits }
|
||||
mngr.ready := clts.map(_.ready).reduce(_&&_)
|
||||
}
|
||||
|
||||
def hookupFinish[M <: LogicalNetworkIO[Finish] : ClassTag](
|
||||
clts: Seq[DecoupledIO[M]],
|
||||
mngr: DecoupledIO[M]) {
|
||||
def hookupFinish[M <: LogicalNetworkIO[Finish]]( clts: Seq[DecoupledIO[M]], mngr: DecoupledIO[M]) {
|
||||
val arb = Module(new RRArbiter(mngr.bits.clone, arbN))
|
||||
arb.io.in zip clts map { case (arb, req) => arb <> req }
|
||||
arb.io.in <> clts
|
||||
arb.io.out <> mngr
|
||||
}
|
||||
}
|
||||
|
||||
/** Abstract base case for any Arbiters that have UncachedTileLinkIOs */
|
||||
abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
|
||||
val io = new Bundle {
|
||||
val in = Vec.fill(arbN){new UncachedTileLinkIO}.flip
|
||||
@ -881,6 +838,7 @@ abstract class UncachedTileLinkIOArbiter(val arbN: Int) extends Module with Tile
|
||||
hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
|
||||
}
|
||||
|
||||
/** Abstract base case for any Arbiters that have cached TileLinkIOs */
|
||||
abstract class TileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike {
|
||||
val io = new Bundle {
|
||||
val in = Vec.fill(arbN){new TileLinkIO}.flip
|
||||
@ -893,31 +851,7 @@ abstract class TileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbi
|
||||
hookupManagerSourceWithId(io.in.map(_.grant), io.out.grant)
|
||||
}
|
||||
|
||||
class HeaderlessUncachedTileLinkIOArbiter(val arbN: Int) extends Module
|
||||
with TileLinkArbiterLike
|
||||
with AppendsArbiterId {
|
||||
val io = new Bundle {
|
||||
val in = Vec.fill(arbN){new HeaderlessUncachedTileLinkIO}.flip
|
||||
val out = new HeaderlessUncachedTileLinkIO
|
||||
}
|
||||
hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
|
||||
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
||||
}
|
||||
|
||||
class HeaderlessTileLinkIOArbiter(val arbN: Int) extends Module
|
||||
with TileLinkArbiterLike
|
||||
with AppendsArbiterId {
|
||||
val io = new Bundle {
|
||||
val in = Vec.fill(arbN){new HeaderlessTileLinkIO}.flip
|
||||
val out = new HeaderlessTileLinkIO
|
||||
}
|
||||
hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
|
||||
hookupClientSourceHeaderless(io.in.map(_.release), io.out.release)
|
||||
hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
|
||||
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
||||
}
|
||||
|
||||
// Appends the port index of the arbiter to the client_xact_id
|
||||
/** Appends the port index of the arbiter to the client_xact_id */
|
||||
trait AppendsArbiterId extends TileLinkArbiterLike {
|
||||
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) =
|
||||
Cat(in.client_xact_id, UInt(id, log2Up(arbN)))
|
||||
@ -926,24 +860,125 @@ trait AppendsArbiterId extends TileLinkArbiterLike {
|
||||
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id(log2Up(arbN)-1,0).toUInt
|
||||
}
|
||||
|
||||
// Uses the client_xact_id as is (assumes it has been set to port index)
|
||||
/** Uses the client_xact_id as is (assumes it has been set to port index) */
|
||||
trait PassesId extends TileLinkArbiterLike {
|
||||
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = in.client_xact_id
|
||||
def managerSourcedClientXactId(in: ManagerSourcedWithId) = in.client_xact_id
|
||||
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id
|
||||
}
|
||||
|
||||
// Overwrites some default client_xact_id with the port idx
|
||||
/** Overwrites some default client_xact_id with the port idx */
|
||||
trait UsesNewId extends TileLinkArbiterLike {
|
||||
def clientSourcedClientXactId(in: ClientSourcedWithId, id: Int) = UInt(id, log2Up(arbN))
|
||||
def managerSourcedClientXactId(in: ManagerSourcedWithId) = UInt(0)
|
||||
def arbIdx(in: ManagerSourcedWithId) = in.client_xact_id
|
||||
}
|
||||
|
||||
// Mix-in id generation traits to make concrete arbiter classes
|
||||
// Now we can mix-in thevarious id-generation traits to make concrete arbiter classes
|
||||
class UncachedTileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends UncachedTileLinkIOArbiter(n) with AppendsArbiterId
|
||||
class UncachedTileLinkIOArbiterThatPassesId(val n: Int) extends UncachedTileLinkIOArbiter(n) with PassesId
|
||||
class UncachedTileLinkIOArbiterThatUsesNewId(val n: Int) extends UncachedTileLinkIOArbiter(n) with UsesNewId
|
||||
class TileLinkIOArbiterThatAppendsArbiterId(val n: Int) extends TileLinkIOArbiter(n) with AppendsArbiterId
|
||||
class TileLinkIOArbiterThatPassesId(val n: Int) extends TileLinkIOArbiter(n) with PassesId
|
||||
class TileLinkIOArbiterThatUsesNewId(val n: Int) extends TileLinkIOArbiter(n) with UsesNewId
|
||||
|
||||
/** Concrete uncached client-side arbiter that appends the arbiter's port id to client_xact_id */
|
||||
class ClientUncachedTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
||||
val io = new Bundle {
|
||||
val in = Vec.fill(arbN){new ClientUncachedTileLinkIO}.flip
|
||||
val out = new ClientUncachedTileLinkIO
|
||||
}
|
||||
hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
|
||||
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
||||
}
|
||||
|
||||
/** Concrete client-side arbiter that appends the arbiter's port id to client_xact_id */
|
||||
class ClientTileLinkIOArbiter(val arbN: Int) extends Module with TileLinkArbiterLike with AppendsArbiterId {
|
||||
val io = new Bundle {
|
||||
val in = Vec.fill(arbN){new ClientTileLinkIO}.flip
|
||||
val out = new ClientTileLinkIO
|
||||
}
|
||||
hookupClientSourceHeaderless(io.in.map(_.acquire), io.out.acquire)
|
||||
hookupClientSourceHeaderless(io.in.map(_.release), io.out.release)
|
||||
hookupManagerSourceBroadcast(io.in.map(_.probe), io.out.probe)
|
||||
hookupManagerSourceHeaderlessWithId(io.in.map(_.grant), io.out.grant)
|
||||
}
|
||||
|
||||
/** Utility trait containing wiring functions to keep track of how many data beats have
|
||||
* been sent or recieved over a particular TileLinkChannel or pair of channels.
|
||||
*
|
||||
* Won't count message types that don't have data.
|
||||
* Used in XactTrackers and FinishUnit.
|
||||
*/
|
||||
trait HasDataBeatCounters {
|
||||
type HasBeat = TileLinkChannel with HasTileLinkBeatId
|
||||
|
||||
/** Returns the current count on this channel and when a message is done
|
||||
* @param inc increment the counter (usually .valid or .fire())
|
||||
* @param data the actual channel data
|
||||
* @param beat count to return for single-beat messages
|
||||
*/
|
||||
def connectDataBeatCounter[S <: TileLinkChannel](inc: Bool, data: S, beat: UInt) = {
|
||||
val multi = data.hasMultibeatData()
|
||||
val (multi_cnt, multi_done) = Counter(inc && multi, data.tlDataBeats)
|
||||
val cnt = Mux(multi, multi_cnt, beat)
|
||||
val done = Mux(multi, multi_done, inc)
|
||||
(cnt, done)
|
||||
}
|
||||
|
||||
/** Counter for beats on outgoing DecoupledIOs */
|
||||
def connectOutgoingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T], beat: UInt = UInt(0)): (UInt, Bool) =
|
||||
connectDataBeatCounter(in.fire(), in.bits, beat)
|
||||
|
||||
/** Returns done but not cnt. Use the addr_beat subbundle instead of cnt for beats on
|
||||
* incoming channels in case of network reordering.
|
||||
*/
|
||||
def connectIncomingDataBeatCounter[T <: TileLinkChannel](in: DecoupledIO[T]): Bool =
|
||||
connectDataBeatCounter(in.fire(), in.bits, UInt(0))._2
|
||||
|
||||
/** Counter for beats on incoming DecoupledIO[LogicalNetworkIO[]]s returns done */
|
||||
def connectIncomingDataBeatCounterWithHeader[T <: TileLinkChannel](in: DecoupledIO[LogicalNetworkIO[T]]): Bool =
|
||||
connectDataBeatCounter(in.fire(), in.bits.payload, UInt(0))._2
|
||||
|
||||
/** If the network might interleave beats from different messages, we need a Vec of counters,
|
||||
* one for every outstanding message id that might be interleaved.
|
||||
*
|
||||
* @param getId mapping from Message to counter id
|
||||
*/
|
||||
def connectIncomingDataBeatCountersWithHeader[T <: TileLinkChannel with HasClientTransactionId](
|
||||
in: DecoupledIO[LogicalNetworkIO[T]],
|
||||
entries: Int,
|
||||
getId: LogicalNetworkIO[T] => UInt): Vec[Bool] = {
|
||||
Vec((0 until entries).map { i =>
|
||||
connectDataBeatCounter(in.fire() && getId(in.bits) === UInt(i), in.bits.payload, UInt(0))._2
|
||||
})
|
||||
}
|
||||
|
||||
/** Provides counters on two channels, as well a meta-counter that tracks how many
|
||||
* messages have been sent over the up channel but not yet responded to over the down channel
|
||||
*
|
||||
* @param max max number of outstanding ups with no down
|
||||
* @param up outgoing channel
|
||||
* @param down incoming channel
|
||||
* @param beat overrides cnts on single-beat messages
|
||||
* @param track whether up's message should be tracked
|
||||
* @return a tuple containing whether their are outstanding messages, up's count,
|
||||
* up's done, down's count, down's done
|
||||
*/
|
||||
def connectTwoWayBeatCounter[T <: TileLinkChannel, S <: TileLinkChannel](
|
||||
max: Int,
|
||||
up: DecoupledIO[T],
|
||||
down: DecoupledIO[S],
|
||||
beat: UInt = UInt(0),
|
||||
track: T => Bool = (t: T) => Bool(true)): (Bool, UInt, Bool, UInt, Bool) = {
|
||||
val cnt = Reg(init = UInt(0, width = log2Up(max+1)))
|
||||
val (up_idx, up_done) = connectDataBeatCounter(up.fire(), up.bits, beat)
|
||||
val (down_idx, down_done) = connectDataBeatCounter(down.fire(), down.bits, beat)
|
||||
val do_inc = up_done && track(up.bits)
|
||||
val do_dec = down_done
|
||||
cnt := Mux(do_dec,
|
||||
Mux(do_inc, cnt, cnt - UInt(1)),
|
||||
Mux(do_inc, cnt + UInt(1), cnt))
|
||||
(cnt > UInt(0), up_idx, up_done, down_idx, down_done)
|
||||
}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user