diff --git a/src/main/scala/diplomacy/SRAM.scala b/src/main/scala/diplomacy/SRAM.scala
index 8add66d4..d0b700f8 100644
--- a/src/main/scala/diplomacy/SRAM.scala
+++ b/src/main/scala/diplomacy/SRAM.scala
@@ -10,9 +10,11 @@ abstract class DiplomaticSRAM(
     beatBytes: Int,
     devName: Option[String])(implicit p: Parameters) extends LazyModule
 {
-  protected val resources = devName
-    .map(new SimpleDevice(_, Seq("sifive,sram0")).reg("mem"))
-    .getOrElse(new MemoryDevice().reg)
+  val device = devName
+    .map(new SimpleDevice(_, Seq("sifive,sram0")))
+    .getOrElse(new MemoryDevice())
+
+  val resources = device.reg("mem")
 
   def bigBits(x: BigInt, tail: List[Boolean] = Nil): List[Boolean] =
     if (x == 0) tail.reverse else bigBits(x >> 1, ((x & 1) == 1) :: tail)