riscv/rocket-chip
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change icache parameters

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This commit is contained in:
Yunsup Lee 2012-03-15 15:35:12 -07:00
parent 72006160dc
commit ba566f246e
1 changed files with 2 additions and 2 deletions
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4
rocket/src/main/scala/top.scala
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@ -17,7 +17,7 @@ class Top() extends Component {
val htif = new rocketHTIF(htif_width, 1) val htif = new rocketHTIF(htif_width, 1)
val cpu = new rocketProc(resetSignal = htif.io.cpu(0).reset); val cpu = new rocketProc(resetSignal = htif.io.cpu(0).reset);
val icache = new rocketICache(128, 2); // 128 sets x 2 ways val icache = new rocketICache(128, 4) // 128 sets x 4 ways (32KB)
val icache_pf = new rocketIPrefetcher(); val icache_pf = new rocketIPrefetcher();
val dcache = new HellaCacheUniproc(); val dcache = new HellaCacheUniproc();
@ -44,7 +44,7 @@ class Top() extends Component {
if (HAVE_VEC) if (HAVE_VEC)
{ {
val vicache = new rocketICache(128, 2); // 128 sets x 2 ways val vicache = new rocketICache(128, 1); // 128 sets x 1 ways (8KB)
arbiter.io.requestor(2) <> vicache.io.mem arbiter.io.requestor(2) <> vicache.io.mem
cpu.io.vimem <> vicache.io.cpu; cpu.io.vimem <> vicache.io.cpu;
} }